OSI 600D Superboard Build

[rubber_jonnie]

Oh, static RAM is easy, it's just like an EPROM which you can write to in terms of wiring things up. No fiddling with RAS and CAS lines or multiplexing in general. It's very simple. Wire up the address lines, wire up the data lines, wire up the chip select and the R/W line and usually Bob's your aunty.

That would be why they're using static RAM, no need for a refresh of multiplexing circuitry.

Indeed, it does make the computer much simpler, and if I understand correctly, it's better for power too.

I don't suppose it would hurt to get a static RAM IC that's 8K and a bit of protoboard and give it a try.

[stephen_usher]

How is the original RAM set up? Banks of two 1Kx4 chips?

If so then the easy solution, instead of having to have a multiplexer chip to generate the high address values from the chip enable on each bank, would be to buy a much larger 64K SRAM chip and just use the bank chip enable as an address line. Wasteful in terms of memory but far simpler to build.

The alternative would be to use a 74LS151 multiplexer to generate the top three bits of the address using the chip enable lines as input.

[rubber_jonnie]

How is the original RAM set up? Banks of two 1Kx4 chips?

If so then the easy solution, instead of having to have a multiplexer chip to generate the high address values from the chip enable on each bank, would be to buy a much larger 64K SRAM chip and just use the bank chip enable as an address line. Wasteful in terms of memory but far simpler to build.

The alternative would be to use a 74LS151 multiplexer to generate the top three bits of the address using the chip enable lines as input.

Yes, 2 banks of 8, 1K x 4bit, so 2 per 1K of RAM.

I really should try doing something like this, it would improve my knowledge and abilities.

[stephen_usher]

So, in that case you would pick up the 8 data lines and 10 address lines from the first bank sockets and the 8 chip enable lines from each bank. Push the chip enable lines through an 8 bit multiplexer to get the top three address lines. Seeing as the chip enable lines are enabled low you need to invert them and then put them through or gates and then invert the result so that if any one of them is low the output enable on the SRAM will be low. You can also pick up the R/W line from one of the sockets too.

So, that would be:

data lines from first pair of sockets -> SRAM chip
address lines from first socket -> SRAM chip
R/W line from first socket -> SRAM chip
8 /OE or /CE lines from each bank -> multiplexer -> top three address lines of SRAM
8 /OE or /CE lines -> inverters -> OR gates -> single line active high if any of the /OE lines low -> inverter -> SRAM /OE.
Keep SRAM /CE line low.

The alternative to the inverters etc. would be a pull-up resistor and eight diodes, anode (or is it cathode?) towards the /OE lines so they can pull down the /OE line. Effectively a parallel active low OR gate. Any one of the /OE lines from the banks can pull the /OE to the SRAM low.

[rubber_jonnie]

So, in that case you would pick up the 8 data lines and 10 address lines from the first bank sockets and the 8 chip enable lines from each bank. Push the chip enable lines through an 8 bit multiplexer to get the top three address lines. Seeing as the chip enable lines are enabled low you need to invert them and then put them through or gates and then invert the result so that if any one of them is low the output enable on the SRAM will be low. You can also pick up the R/W line from one of the sockets too.

So, that would be:

data lines from first pair of sockets -> SRAM chip
address lines from first socket -> SRAM chip
R/W line from first socket -> SRAM chip
8 /OE or /CE lines from each bank -> multiplexer -> top three address lines of SRAM
8 /OE or /CE lines -> inverters -> OR gates -> single line active high if any of the /OE lines low -> inverter -> SRAM /OE.
Keep SRAM /CE line low.

The alternative to the inverters etc. would be a pull-up resistor and eight diodes, anode (or is it cathode?) towards the /OE lines so they can pull down the /OE line. Effectively a parallel active low OR gate. Any one of the /OE lines from the banks can pull the /OE to the SRAM low.

Cool thanks, that's interesting :)

I will give it a go once I have the basic machine running as I have enough RAM for that I think.

[rubber_jonnie]

OK, EEPROMS have arrived :) Also one of the missing 74LS ICs and the fuse holders (Bit late for those, but I do have spares for the parts bin now.

Good job I ordered 10 as 2 seem to be dead!! The rest test just fine.

The machine requires 6, so that leaves me 2 spares just in case. Always a risk when ordering from AliExpress though, but a lot cheaper then I could find elsewhere at £1.27 a chip rather than about £10.

Need to dig out the ROM files next and get them programmed up.

[HigashiJun]

Waiting for the final result !

8-)

[rubber_jonnie]

Waiting for the final result !

8-)

You and me both!!!

[rubber_jonnie]

ROMs programmed and Installed :)

[rubber_jonnie]

So, in that case you would pick up the 8 data lines and 10 address lines from the first bank sockets and the 8 chip enable lines from each bank. Push the chip enable lines through an 8 bit multiplexer to get the top three address lines. Seeing as the chip enable lines are enabled low you need to invert them and then put them through or gates and then invert the result so that if any one of them is low the output enable on the SRAM will be low. You can also pick up the R/W line from one of the sockets too.

So, that would be:

data lines from first pair of sockets -> SRAM chip
address lines from first socket -> SRAM chip
R/W line from first socket -> SRAM chip
8 /OE or /CE lines from each bank -> multiplexer -> top three address lines of SRAM
8 /OE or /CE lines -> inverters -> OR gates -> single line active high if any of the /OE lines low -> inverter -> SRAM /OE.
Keep SRAM /CE line low.

The alternative to the inverters etc. would be a pull-up resistor and eight diodes, anode (or is it cathode?) towards the /OE lines so they can pull down the /OE line. Effectively a parallel active low OR gate. Any one of the /OE lines from the banks can pull the /OE to the SRAM low.

Hmm, I have a 6116 2K x 8bit static RAM in my parts drawer, might work as a test.