exxos's DFB1 trials

[Badwolf]

I did actually try that earlier in fact and it made no odds..

Ah.

Given how long it takes to swich 'down' (there's a dropped cycle in there), perhaps it's actually too slow for the FPU?

Maybe we need to delay FPUCS until the switch has definitely happened? There's a signal called 'clock_block' which is intended for this purpose, but I don't recall if it's active high or active low.

BW

[dml]

So for whatever reason the FPU is not stable with half OSC speed to the CPU. Indeed 50MHz seems to aggravate the problem so it is certainly possible the FPU is only capable of 40MHz..

From my own experiments I was able to get several FPUs to run at 40 (including some rated at 25 or 33) but never got any to run at 50 (or even 48) - including those marked for 40. I think they can go a bit beyond 40 before things start to fail.

The highest rated chip I have is 40MHz, don't have any rated for 50 to try.


Anyway at 50MHz I think you're hitting limits for the IC irrespective of DFB1.

[exxos]

I think the FPU is always intended to run faster than the CPU. I experimentally decided it could run on a slower clock, but only down to about half the CPU frequency (makes sense -- if DSACK[x] is asserted too long, CPU confusion could abound).

BUT, perhaps that is really really marginal and I've made a boo-boo there.

It does seem like the FPU need to run faster than the CPU currently.. Let me retest to make sure..

So 40MHz clock WITH OPTION2 works, without OPTION2 crashes on first test. So assume with OPTION2, the CPU is 16MHz and FPU 40MHz.

Given how long it takes to switch 'down' (there's a dropped cycle in there), perhaps it's actually too slow for the FPU?

Maybe we need to delay FPUCS until the switch has definitely happened? There's a signal called 'clock_block' which is intended for this purpose, but I don't recall if it's active high or active low.

I did delay FPUCS, but that was when it started working and I took it out because it was seemingly OPTION2 which made it work.

It is rather puzzling.. If running the CPU slower works, then maybe the FPU is keeping data on the bus for a lot longer than we think? and trips up the next cycle on the CPU when running at higher speed?

[exxos]

From my own experiments I was able to get several FPUs to run at 40 (including some rated at 25 or 33) but never got any to run at 50 (or even 48) - including those marked for 40. I think they can go a bit beyond 40 before things start to fail.

The highest rated chip I have is 40MHz, don't have any rated for 50 to try.

Anyway at 50MHz I think you're hitting limits for the IC irrespective of DFB1.

Yes I think that is the case. From here on out and is going to use a 40MHz OSC to rule out that problem for now.

[exxos]

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu ), .C( OSCCLK_2 ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu ), .C( OSCCLK ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Made no odds.

Swapping these made no odds either. (tried with and without the above code)

Code: Select all

wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
//wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too)

EDIT:

Also tried

Code: Select all

wire FPUDSACK2;
FDCP ff_fpu1( .D( FPUDSACK ), .C( OSCCLK_2 ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPUDSACK2) );
wire [1:0] FPU_DSACK_INT = fpu | FPUDSACK2 | FPUDSACK;

[Badwolf]

Swapping these made no odds either. (tried with and without the above code)

Code: Select all

wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
//wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too)

Maybe try something like this with the top one of these:-

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

That's gating fpu with clockblock (might have to do ~clock_block, I forget which way it's active) and only sampling on the 16MHz clock instead of the 40,

(the idea is to only allow CS once the clock switch down has completed)

BW

[dml]

From the '882 datasheet...

"Since the bus is asynchronous, the MC68882 need not run the same clock speed as the main processor.
Total system performance may therefore be customized. For a given CPU performance requirement,
the floating-point performance can be selected to meet Particular Price/performance specifications,
running the MC68882 at slower (or faster) clock speeds than the MPU clock."

I don't see anything indicating limits on the clock ratio in either direction, just the min/max times in the table mentioned earlier and some stuff in the async read/write diagram.

[exxos]

From the '882 datasheet...

"Since the bus is asynchronous, the MC68882 need not run the same clock speed as the main processor.
Total system performance may therefore be customized. For a given CPU performance requirement,
the floating-point performance can be selected to meet Particular Price/performance specifications,
running the MC68882 at slower (or faster) clock speeds than the MPU clock."

I don't see anything indicating limits on the clock ratio in either direction, just the min/max times in the table mentioned earlier and some stuff in the async read/write diagram.

Interesting...

[exxos]

Swapping these made no odds either. (tried with and without the above code)

Code: Select all

wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
//wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too)

Maybe try something like this with the top one of these:-

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

That's gating fpu with clockblock (might have to do ~clock_block, I forget which way it's active) and only sampling on the 16MHz clock instead of the 40,

(the idea is to only allow CS once the clock switch down has completed)

BW

No odds.

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Code: Select all

//wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too

This one crashes as soon as the program loads.

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Code: Select all

wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
//wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too

Not sure I can really try anything else out as I am out of ideas. Also my hands are starting to hurt again so will have to call it a day for now anyway :(

[Badwolf]

No odds.

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Code: Select all

//wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too

This one crashes as soon as the program loads.

Code: Select all

wire FPU_2;
FDCP ff_fpu1( .D( fpu | clock_block ), .C( XCPUCLK  ), .CLR(1'b0), .PRE( 1'b0 ), .Q(FPU_2) );
assign FPUCS = FPU_2 | fpu | AS;

Code: Select all

//wire lowspeed = DISABLE_FAST & resetblock & fpu & ( AS | ~ttram_access | ~rom_access ) & clockholdoff ; // low active (rom access here too)
wire lowspeed = DISABLE_FAST & resetblock & ( AS | ~ttram_access | ~rom_access | ~fpu ) & clockholdoff ; // low active (rom access here too

You're using the wrong lowspeed there. Would only work with the top one, but also I don't see the difference between the two you quoted. Presumably one is meant to be with | clock_block and the other with | ~clock_block?

Not sure I can really try anything else out as I am out of ideas. Also my hands are starting to hurt again so will have to call it a day for now anyway :(

Yeah, no worries. You've actually got a lot further than I did!

I might do some more firmware experiments later and hack in more capacitance. My board works fine at 25MHz, but if I could get it up to 36 or 40 that would be great and help prove a point.

BW