ST SHIFTER operation ?

[exxos]

Without checking, I'm afraid that the GLUE will only activate /CS for the first 17 of the 32 available addresses. If you try accessing the registers at 0xFF8262-0xFF826E frome code on an STF, do you get a bus error or will the /CS pin on the Shifter be pulled low?

17 is all I need, palette registers and control register. I was just saying the address space is 32 long, even though the shifter won't use them all.

Of course different on the TT, would need its 256 palette registers there, and need a bunch of address decoding etc..

[Smonson]

Without checking, I'm afraid that the GLUE will only activate /CS for the first 17 of the 32 available addresses. If you try accessing the registers at 0xFF8262-0xFF826E frome code on an STF, do you get a bus error or will the /CS pin on the Shifter be pulled low?

If that's the case, a simple way around it is to use register 0 for palette index and register 1 for the register itself, instead of colour 0 and 1, when in 256-colour mode.

[exxos]

Small circuit update.. The registers select blocks now wired up..

I think the only thing which is not added so for, is the control register.. Currently everything on this circuit is wired for low resolution. Once the control register is added, the other resolutions will then be supported. Though I am not adding anything else this circuit now until the basic low resolution designs tested. Otherwise circuit is just going to be too complicated to debug if I add other things at this stage.

shifter_copy.jpg

EDIT:

A few typo fixes later..

Capture.JPG

EDIT2:
I updated the 373 latches into a single block file, basically together 16 bit version. While I was messing about, I remove the tri-state outputs these latches, thinking it would reduce the logic count. But it seems it did not make any difference and the logic out as exactly as before.

So either my test wasn't good enough, or the compiler is actually really good in optimising circuits.

[exxos]

shifter_copy.jpg

Added in the control register. It does not do actual functions yet, but the register should at least be readable and writable to.

[Smonson]

Without checking, I'm afraid that the GLUE will only activate /CS for the first 17 of the 32 available addresses. If you try accessing the registers at 0xFF8262-0xFF826E frome code on an STF, do you get a bus error or will the /CS pin on the Shifter be pulled low?

I tested this tonight by adding extra registers in my FPGA-shifter, and they can be written and read back OK at all 32 addresses.