REV 3 - REV 5 - The beginning (ST536)

[exxos]

Its been running fine with slow skew and 330R on the clock and 5.20V on a SR98. Now i've changed back to fast slew for the hell of it and... something is amiss :lol: who can spot it ?

This is without blitter

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With blitter..

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EDIT:

I also tried 270R and with slow slew TTram isn't found again ! There must be some ultra tight borderline timing somewhere..

[exxos]

This is madness...

BLUE = CPU clock (50MHz)
YELLOW = SDRAM CLOCK (100MHz)


270R load resistors on the CPU clock...

IMG_4050.JPG

330R load...

IMG_4051.JPG

How is that even possible ?!


Slow slew vs fast slew...

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It looks like the PLD is really struggling to drive the CPU clock. Even with 500R load its still struggling on the rise.


With no load resistor at all (fast slew still)

IMG_4054.JPG

I think I need to get some series resistance in the clocks like I did with the STE536.. but that's not to simple..

[exxos]

Managed to hack on a 500R trimmer..

IMG_4058.JPG

Now regardless of trimmer setting, or parallel loading, fast or slow slew , its totally unstable again . Can't bloody win with the thing ! :headbang:

It be useful if someone could measure a original TF536 SDRAM clock and CPU clock to see what its like with the 10ns PLD.

[PhilC]

@exxos will try and get that done tomorrow.

[exxos]

@exxos will try and get that done tomorrow.

Thanks. Be super useful.

[exxos]

Decided to hardwire the SDRAM clock back to the master OSC again.. and its booted up fine (need to do more tests)

This was the clocks PLD driven..

BLUE = CPU clock (50MHz)
YELLOW = SDRAM CLOCK (100MHz)

IMG_4061.JPG

Master OSC driven..

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Not massive change.. but clear something has changed on the rise and fall... More voltage output as well.. Those changes are enough to make or break it it seems :roll:

I mean maybe the timing report wasn't lying afterall ... (max clock)

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EDIT:

Now with about 250R in series with the clock...

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GB6 ran fine now as well..

So i'm leaning towards the PLD can't drive 100MHz SDRAM clock reliably now.. I mean it struggles to even hit 2v p-p a lot of the time. The min voltage on the SDRAM inputs is 2V !

Its running YAARTTT.. Will leave it on for a bit and see what happens now...

[exxos]

Left it on overnight and it has been working fine again...

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Tests are slow slew and 5.20v with a SR98.. Problem is on the ST536 the voltage ends up at 5.05v when the floppy turns on..
I'm going to try one of my PSUs next. 5.05v on the PSU and 5.02v on the 536..

One very interesting observation is that ST Ram speed has gone up now from 114% to 116%... TTram speed also gone up..

Problem is.. Since swapping PSU.. And swapping back again.. Its unstable again.. So powering down seems to upset something.. Now it's working again... I lowered the clock series resistance..

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One thing I just found out is that the clock pin on the CPU is very sensitive to the point where if I even touch it with the meter probe it locks up and it does not seem to matter what resistance is there either.

EDIT:

If I put the 330R on the PLD and then have ~68R in series with the CPU clock its way more stable that way. So those mods will go into the next board respin. Previous boards can hack the 330R on the back of the CPU for now.

[stephen_usher]

It's not a grounding issue is it?

[exxos]

It's not a grounding issue is it?

From what to what ?

[stephen_usher]

Between the clock generation and the CPU.

If touching the clock pin skews the voltage enough to upset things then my first suspect would be the grounding of the clock generator as the capacitance of the body is likely to cause a DC offset. Just a thought.

The other alternative is that the drive circuitry just can't push a lot of electrons and so touching the pin basically pulls it down to zero. Putting a resistor on the line would just make this worse if this is the issue.

P.S. To generate the clocks, one being half the other, have you thought about pushing the crystal output into a couple of high speed inverter gates (50MHz) and a high speed flip-flop (25MHz), which will probably have similar latency. You'd then get logic level square clock signals which are far less influenced by chip voltage level switching tolerances and hysteresis.