Are you sure you're decoding the access? (AS_MOBO versus AS_030)
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Are you sure you're decoding the access? (AS_MOBO versus AS_030)


Well done!exxos wrote: 21 Apr 2022 15:23 So blitter is actually faster.. But "worthwhile faster" maybe not so much.

I am not sure that DTACK would matter though ? I have not checked, but I assume that DTACK on the STE goes low about 20-40ns after /AS low. My DTACK will go low after about 30ns.. Even so these are open collector things, so even if both go low or one or the other it does not matter. Also, everything is still running at stock speeds anyway at that point. So any bus master doesn't care about the timing.Badwolf wrote: 21 Apr 2022 16:16 but you'd now need to have a separate STE firmware (or perhaps a register to turn this on?) that doesn't assert DTACK. Not sure there's a net benefit to you as a seller in that case.

I'll bow to your superior knowledge of the glue logic on the ST boards -- but are you 100% sure DTACK is only ever driven open drain by the motherboard? If so, then yeah, it should be safe.exxos wrote: 21 Apr 2022 16:22 I am not sure that DTACK would matter though ? I have not checked, but I assume that DTACK on the STE goes low about 20-40ns after /AS low. My DTACK will go low after about 30ns.. Even so these are open collector things, so even if both go low or one or the other it does not matter. Also, everything is still running at stock speeds anyway at that point. So any bus master doesn't care about the timing.

Nothing *should* drive it high. If it does, then another suckage of the system I guess. But even so, any chips doing so, should/could only be doing it when it has its own CS signal asserted ? If something is driving DTACK high otherwise, then I don't see how the system could ever even work.Badwolf wrote: 21 Apr 2022 16:41 are you 100% sure DTACK is only ever driven open drain by the motherboard? If so, then yeah, it should be safe.

MFP's DTACK is not open drain, it is tri-state active push pull. Which means it might drive actively high for a short time, but, of course, only while selected.exxos wrote: 21 Apr 2022 16:49 Nothing *should* drive it high. If it does, then another suckage of the system I guess. But even so, any chips doing so, should/could only be doing it when it has its own CS signal asserted ? If something is driving DTACK high otherwise, then I don't see how the system could ever even work.
At worst it could only be if AS=1 then DTACK=1. At which point we don't care anyway ? If DTACK is still driving high when /AS goes low, then that would be shorting stuff out "from stock". I don't think thats the case as DTACK generally goes low 20-40ns after /AS goes low. My timing doesn't issue it right away, it would still be at least 30ns. So it would pretty much match the chipset timing anyway.
I would have course be very interested if you or anyone else for that matter has evidence to show that some chip on the board is driving DTACK high rather than using the proper method of open collector. I know people have over the years have suggested exactly the same but I have never seen anyone actually ever prove it.
GLUE asserts BERR after 64 cycles. This is the same in the STF or the STE.Badwolf wrote: 21 Apr 2022 14:57 So what happens on the STE if nothing issues DTACK after (I think it's about) 100 cycles, BERR is issued.
Blitter doesn't care whether it's DTACK or BERR it just sees end of cycle and carries on. So ends up running ~50x slower than normal. I presume it's the same on the STF chipset.

:thanksyellow:
ijor wrote: 21 Apr 2022 17:34 MFP's DTACK is not open drain, it is tri-state active push pull. Which means it might drive actively high for a short time, but, of course, only while selected.

Code: Select all
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
581 but only 144 left after allocating other resources.Code: Select all
************************** Errors and Warnings ***************************
INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 1 and input limit: 1
ERROR:Cpld:837 - Insufficient number of macrocells. The design needs at least
581 but only 144 left after allocating other resources.
ERROR:Cpld:868 - Cannot fit the design into any of the specified devices with
the selected implementation options.
************************* Mapped Resource Summary **************************
No logic has been mapped.
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
61 /144 ( 42%) 84 /720 ( 12%) 97 /432 ( 22%) 18 /144 ( 12%) 108/117 ( 92%)
** Function Block Resources **
Function Mcells FB Inps Pterms IO
Block Used/Tot Used/Tot Used/Tot Used/Tot
FB1 14/18 23/54 15/90 15/15*
FB2 15/18 17/54 12/90 15/15*
FB3 7/18 9/54 17/90 8/15
FB4 1/18 0/54 0/90 15/15*
FB5 9/18 22/54 21/90 12/14
FB6 0/18 0/54 0/90 13/13*
FB7 7/18 14/54 10/90 15/15*
FB8 8/18 12/54 9/90 15/15*
----- ----- ----- -----
61/144 97/432 84/720 108/117
* - Resource is exhausted
************************* Summary of UnMapped Logic ************************
** 520 Buried Nodes **
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_AND$1026403 1 2
$OpTx$BIN_AND$1026414 1 2
$OpTx$BIN_AND$1026415 1 2
$OpTx$BIN_AND$1026416 1 2
$OpTx$BIN_AND$1026417 1 2
$OpTx$BIN_AND$1026418 1 2
$OpTx$BIN_AND$1026419 1 2
$OpTx$BIN_AND$1026420 1 2
$OpTx$BIN_AND$1026424 1 2
$OpTx$BIN_AND$1026426 1 2
$OpTx$BIN_AND$1026427 1 2
$OpTx$BIN_AND$1026433 1 2
$OpTx$BIN_AND$1026435 1 2
$OpTx$BIN_AND$1026437 1 2
$OpTx$BIN_AND$1026443 1 2
$OpTx$BIN_AND$1026447 1 2
$OpTx$BIN_AND$1026448 1 2
$OpTx$BIN_AND$1026452 1 2
$OpTx$BIN_AND$1026454 1 2
$OpTx$BIN_AND$1026462 1 2
$OpTx$BIN_AND$1026463 1 2
$OpTx$BIN_AND$1026465 1 2
$OpTx$BIN_AND$1026466 1 2
$OpTx$BIN_AND$1026467 1 2
$OpTx$BIN_AND$1026481 1 2
$OpTx$BIN_AND$1026483 1 2
$OpTx$BIN_AND$1026521 1 2
$OpTx$BIN_AND$1026522 1 2
$OpTx$BIN_AND$1026523 1 2
$OpTx$BIN_AND$1026525 1 2
$OpTx$BIN_AND$1026526 1 2
$OpTx$BIN_AND$1026527 1 2
$OpTx$BIN_AND$1026531 1 2
$OpTx$BIN_AND$1026532 1 2
$OpTx$BIN_AND$1026534 1 2
$OpTx$BIN_AND$1026554 1 2
$OpTx$BIN_AND$1026558 1 2
$OpTx$BIN_AND$1026578 1 2
$OpTx$BIN_AND$1026579 1 2
$OpTx$BIN_AND$1026594 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_AND$1026614 1 2
$OpTx$BIN_AND$1026615 1 2
$OpTx$BIN_AND$1026649 1 2
$OpTx$BIN_AND$1026650 1 2
$OpTx$BIN_AND$1026651 1 2
$OpTx$BIN_AND$1026663 1 2
$OpTx$BIN_AND$1026664 1 2
$OpTx$BIN_AND$1026681 1 2
$OpTx$BIN_AND$1026682 1 2
$OpTx$BIN_AND$1026683 1 2
$OpTx$BIN_AND$1026684 1 2
$OpTx$BIN_AND$1026687 1 2
$OpTx$BIN_AND$1026689 1 2
$OpTx$BIN_AND$1026691 1 2
$OpTx$BIN_AND$1026692 1 2
$OpTx$BIN_AND$1026701 1 2
$OpTx$BIN_AND$1026702 1 2
$OpTx$BIN_AND$1026704 1 2
$OpTx$BIN_AND$1026711 1 2
$OpTx$BIN_AND$1026723 1 2
$OpTx$BIN_AND$1026724 1 2
$OpTx$BIN_AND$1026751 1 2
$OpTx$BIN_AND$1026755 1 2
$OpTx$BIN_AND$1026757 1 2
$OpTx$BIN_AND$1026758 1 2
$OpTx$BIN_AND$1026759 1 2
$OpTx$BIN_AND$1026761 1 2
$OpTx$BIN_AND$1026765 1 2
$OpTx$BIN_AND$1026766 1 2
$OpTx$BIN_AND$1026767 1 2
$OpTx$BIN_AND$1026769 1 2
$OpTx$BIN_AND$1026770 1 2
$OpTx$BIN_AND$1026773 1 2
$OpTx$BIN_AND$1026775 1 2
$OpTx$BIN_AND$1026776 1 2
$OpTx$BIN_AND$1026778 1 2
$OpTx$BIN_AND$1026779 1 2
$OpTx$BIN_AND$1026784 1 2
$OpTx$BIN_AND$1026788 1 2
$OpTx$BIN_AND$1026789 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_AND$1026790 1 2
$OpTx$BIN_AND$1026791 1 2
$OpTx$BIN_AND$1026792 1 2
$OpTx$BIN_AND$1026794 1 2
$OpTx$BIN_AND$1026796 1 2
$OpTx$BIN_AND$1026797 1 2
$OpTx$BIN_AND$1026798 1 2
$OpTx$BIN_AND$1026799 1 2
$OpTx$BIN_AND$1026800 1 2
$OpTx$BIN_AND$1026801 1 2
$OpTx$BIN_AND$1026802 1 2
$OpTx$BIN_AND$1026803 1 2
$OpTx$BIN_AND$1026804 1 2
$OpTx$BIN_AND$1026805 1 2
$OpTx$BIN_AND$1026806 1 2
$OpTx$BIN_AND$1026807 1 2
$OpTx$BIN_AND$1026808 1 2
$OpTx$BIN_AND$1026809 1 2
$OpTx$BIN_AND$1026810 1 2
$OpTx$BIN_STEP$1026399 1 2
$OpTx$BIN_STEP$1026400 1 2
$OpTx$BIN_STEP$1026401 1 2
$OpTx$BIN_STEP$1026402 1 2
$OpTx$BIN_STEP$1026405 1 2
$OpTx$BIN_STEP$1026406 1 2
$OpTx$BIN_STEP$1026407 1 2
$OpTx$BIN_STEP$1026408 1 2
$OpTx$BIN_STEP$1026409 1 2
$OpTx$BIN_STEP$1026410 1 2
$OpTx$BIN_STEP$1026411 1 2
$OpTx$BIN_STEP$1026412 1 2
$OpTx$BIN_STEP$1026413 1 2
$OpTx$BIN_STEP$1026422 1 2
$OpTx$BIN_STEP$1026423 1 2
$OpTx$BIN_STEP$1026429 1 2
$OpTx$BIN_STEP$1026430 1 2
$OpTx$BIN_STEP$1026431 1 2
$OpTx$BIN_STEP$1026432 1 2
$OpTx$BIN_STEP$1026439 1 2
$OpTx$BIN_STEP$1026440 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026441 1 2
$OpTx$BIN_STEP$1026442 1 2
$OpTx$BIN_STEP$1026445 1 2
$OpTx$BIN_STEP$1026446 1 2
$OpTx$BIN_STEP$1026450 1 2
$OpTx$BIN_STEP$1026451 1 2
$OpTx$BIN_STEP$1026456 1 2
$OpTx$BIN_STEP$1026457 1 2
$OpTx$BIN_STEP$1026458 1 2
$OpTx$BIN_STEP$1026459 1 2
$OpTx$BIN_STEP$1026460 1 2
$OpTx$BIN_STEP$1026461 1 2
$OpTx$BIN_STEP$1026469 1 2
$OpTx$BIN_STEP$1026470 1 2
$OpTx$BIN_STEP$1026471 1 2
$OpTx$BIN_STEP$1026472 1 2
$OpTx$BIN_STEP$1026473 1 2
$OpTx$BIN_STEP$1026474 1 2
$OpTx$BIN_STEP$1026475 1 2
$OpTx$BIN_STEP$1026476 1 2
$OpTx$BIN_STEP$1026477 1 2
$OpTx$BIN_STEP$1026478 1 2
$OpTx$BIN_STEP$1026479 1 2
$OpTx$BIN_STEP$1026480 1 2
$OpTx$BIN_STEP$1026485 1 2
$OpTx$BIN_STEP$1026486 1 2
$OpTx$BIN_STEP$1026487 1 2
$OpTx$BIN_STEP$1026488 1 2
$OpTx$BIN_STEP$1026489 1 2
$OpTx$BIN_STEP$1026490 1 2
$OpTx$BIN_STEP$1026491 1 2
$OpTx$BIN_STEP$1026492 1 2
$OpTx$BIN_STEP$1026493 1 2
$OpTx$BIN_STEP$1026494 1 2
$OpTx$BIN_STEP$1026495 1 2
$OpTx$BIN_STEP$1026496 1 2
$OpTx$BIN_STEP$1026497 1 2
$OpTx$BIN_STEP$1026498 1 2
$OpTx$BIN_STEP$1026499 1 2
$OpTx$BIN_STEP$1026500 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026501 1 2
$OpTx$BIN_STEP$1026502 1 2
$OpTx$BIN_STEP$1026503 1 2
$OpTx$BIN_STEP$1026504 1 2
$OpTx$BIN_STEP$1026505 1 2
$OpTx$BIN_STEP$1026506 1 2
$OpTx$BIN_STEP$1026507 1 2
$OpTx$BIN_STEP$1026508 1 2
$OpTx$BIN_STEP$1026509 1 2
$OpTx$BIN_STEP$1026510 1 2
$OpTx$BIN_STEP$1026511 1 2
$OpTx$BIN_STEP$1026512 1 2
$OpTx$BIN_STEP$1026513 1 2
$OpTx$BIN_STEP$1026514 1 2
$OpTx$BIN_STEP$1026515 1 2
$OpTx$BIN_STEP$1026516 1 2
$OpTx$BIN_STEP$1026517 1 2
$OpTx$BIN_STEP$1026518 1 2
$OpTx$BIN_STEP$1026519 1 2
$OpTx$BIN_STEP$1026520 1 2
$OpTx$BIN_STEP$1026529 1 2
$OpTx$BIN_STEP$1026530 1 2
$OpTx$BIN_STEP$1026536 1 2
$OpTx$BIN_STEP$1026537 1 2
$OpTx$BIN_STEP$1026538 1 2
$OpTx$BIN_STEP$1026539 1 2
$OpTx$BIN_STEP$1026540 1 2
$OpTx$BIN_STEP$1026541 1 2
$OpTx$BIN_STEP$1026542 1 2
$OpTx$BIN_STEP$1026543 1 2
$OpTx$BIN_STEP$1026544 1 2
$OpTx$BIN_STEP$1026545 1 2
$OpTx$BIN_STEP$1026546 1 2
$OpTx$BIN_STEP$1026547 1 2
$OpTx$BIN_STEP$1026548 1 2
$OpTx$BIN_STEP$1026549 1 2
$OpTx$BIN_STEP$1026550 1 2
$OpTx$BIN_STEP$1026551 1 2
$OpTx$BIN_STEP$1026552 1 2
$OpTx$BIN_STEP$1026553 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026556 1 2
$OpTx$BIN_STEP$1026557 1 2
$OpTx$BIN_STEP$1026560 1 2
$OpTx$BIN_STEP$1026561 1 2
$OpTx$BIN_STEP$1026562 1 2
$OpTx$BIN_STEP$1026563 1 2
$OpTx$BIN_STEP$1026564 1 2
$OpTx$BIN_STEP$1026565 1 2
$OpTx$BIN_STEP$1026566 1 2
$OpTx$BIN_STEP$1026567 1 2
$OpTx$BIN_STEP$1026568 1 2
$OpTx$BIN_STEP$1026569 1 2
$OpTx$BIN_STEP$1026570 1 2
$OpTx$BIN_STEP$1026571 1 2
$OpTx$BIN_STEP$1026572 1 2
$OpTx$BIN_STEP$1026573 1 2
$OpTx$BIN_STEP$1026574 1 2
$OpTx$BIN_STEP$1026575 1 2
$OpTx$BIN_STEP$1026576 1 2
$OpTx$BIN_STEP$1026577 1 2
$OpTx$BIN_STEP$1026581 1 2
$OpTx$BIN_STEP$1026582 1 2
$OpTx$BIN_STEP$1026583 1 2
$OpTx$BIN_STEP$1026584 1 2
$OpTx$BIN_STEP$1026585 1 2
$OpTx$BIN_STEP$1026586 1 2
$OpTx$BIN_STEP$1026587 1 2
$OpTx$BIN_STEP$1026588 1 2
$OpTx$BIN_STEP$1026589 1 2
$OpTx$BIN_STEP$1026590 1 2
$OpTx$BIN_STEP$1026591 1 2
$OpTx$BIN_STEP$1026592 1 2
$OpTx$BIN_STEP$1026593 1 2
$OpTx$BIN_STEP$1026596 1 2
$OpTx$BIN_STEP$1026597 1 2
$OpTx$BIN_STEP$1026598 1 2
$OpTx$BIN_STEP$1026599 1 2
$OpTx$BIN_STEP$1026600 1 2
$OpTx$BIN_STEP$1026601 1 2
$OpTx$BIN_STEP$1026602 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026603 1 2
$OpTx$BIN_STEP$1026604 1 2
$OpTx$BIN_STEP$1026605 1 2
$OpTx$BIN_STEP$1026606 1 2
$OpTx$BIN_STEP$1026607 1 2
$OpTx$BIN_STEP$1026608 1 2
$OpTx$BIN_STEP$1026609 1 2
$OpTx$BIN_STEP$1026610 1 2
$OpTx$BIN_STEP$1026611 1 2
$OpTx$BIN_STEP$1026612 1 2
$OpTx$BIN_STEP$1026613 1 2
$OpTx$BIN_STEP$1026617 1 2
$OpTx$BIN_STEP$1026618 1 2
$OpTx$BIN_STEP$1026619 1 2
$OpTx$BIN_STEP$1026620 1 2
$OpTx$BIN_STEP$1026621 1 2
$OpTx$BIN_STEP$1026622 1 2
$OpTx$BIN_STEP$1026623 1 2
$OpTx$BIN_STEP$1026624 1 2
$OpTx$BIN_STEP$1026625 1 2
$OpTx$BIN_STEP$1026626 1 2
$OpTx$BIN_STEP$1026627 1 2
$OpTx$BIN_STEP$1026628 1 2
$OpTx$BIN_STEP$1026629 1 2
$OpTx$BIN_STEP$1026630 1 2
$OpTx$BIN_STEP$1026631 1 2
$OpTx$BIN_STEP$1026632 1 2
$OpTx$BIN_STEP$1026633 1 2
$OpTx$BIN_STEP$1026634 1 2
$OpTx$BIN_STEP$1026635 1 2
$OpTx$BIN_STEP$1026636 1 2
$OpTx$BIN_STEP$1026637 1 2
$OpTx$BIN_STEP$1026638 1 2
$OpTx$BIN_STEP$1026639 1 2
$OpTx$BIN_STEP$1026640 1 2
$OpTx$BIN_STEP$1026641 1 2
$OpTx$BIN_STEP$1026642 1 2
$OpTx$BIN_STEP$1026643 1 2
$OpTx$BIN_STEP$1026644 1 2
$OpTx$BIN_STEP$1026645 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026646 1 2
$OpTx$BIN_STEP$1026647 1 2
$OpTx$BIN_STEP$1026648 1 2
$OpTx$BIN_STEP$1026653 1 2
$OpTx$BIN_STEP$1026654 1 2
$OpTx$BIN_STEP$1026655 1 2
$OpTx$BIN_STEP$1026656 1 2
$OpTx$BIN_STEP$1026657 1 2
$OpTx$BIN_STEP$1026658 1 2
$OpTx$BIN_STEP$1026659 1 2
$OpTx$BIN_STEP$1026660 1 2
$OpTx$BIN_STEP$1026661 1 2
$OpTx$BIN_STEP$1026662 1 2
$OpTx$BIN_STEP$1026666 1 2
$OpTx$BIN_STEP$1026667 1 2
$OpTx$BIN_STEP$1026668 1 2
$OpTx$BIN_STEP$1026669 1 2
$OpTx$BIN_STEP$1026670 1 2
$OpTx$BIN_STEP$1026671 1 2
$OpTx$BIN_STEP$1026672 1 2
$OpTx$BIN_STEP$1026673 1 2
$OpTx$BIN_STEP$1026674 1 2
$OpTx$BIN_STEP$1026675 1 2
$OpTx$BIN_STEP$1026676 1 2
$OpTx$BIN_STEP$1026677 1 2
$OpTx$BIN_STEP$1026678 1 2
$OpTx$BIN_STEP$1026679 1 2
$OpTx$BIN_STEP$1026680 1 2
$OpTx$BIN_STEP$1026686 1 2
$OpTx$BIN_STEP$1026694 1 2
$OpTx$BIN_STEP$1026695 1 2
$OpTx$BIN_STEP$1026696 1 2
$OpTx$BIN_STEP$1026697 1 2
$OpTx$BIN_STEP$1026698 1 2
$OpTx$BIN_STEP$1026699 1 2
$OpTx$BIN_STEP$1026700 1 2
$OpTx$BIN_STEP$1026706 1 2
$OpTx$BIN_STEP$1026707 1 2
$OpTx$BIN_STEP$1026708 1 2
$OpTx$BIN_STEP$1026709 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026710 1 2
$OpTx$BIN_STEP$1026713 1 2
$OpTx$BIN_STEP$1026714 1 2
$OpTx$BIN_STEP$1026715 1 2
$OpTx$BIN_STEP$1026716 1 2
$OpTx$BIN_STEP$1026717 1 2
$OpTx$BIN_STEP$1026718 1 2
$OpTx$BIN_STEP$1026719 1 2
$OpTx$BIN_STEP$1026720 1 2
$OpTx$BIN_STEP$1026721 1 2
$OpTx$BIN_STEP$1026722 1 2
$OpTx$BIN_STEP$1026726 1 2
$OpTx$BIN_STEP$1026727 1 2
$OpTx$BIN_STEP$1026728 1 2
$OpTx$BIN_STEP$1026729 1 2
$OpTx$BIN_STEP$1026730 1 2
$OpTx$BIN_STEP$1026731 1 2
$OpTx$BIN_STEP$1026732 1 2
$OpTx$BIN_STEP$1026733 1 2
$OpTx$BIN_STEP$1026734 1 2
$OpTx$BIN_STEP$1026735 1 2
$OpTx$BIN_STEP$1026736 1 2
$OpTx$BIN_STEP$1026737 1 2
$OpTx$BIN_STEP$1026738 1 2
$OpTx$BIN_STEP$1026739 1 2
$OpTx$BIN_STEP$1026740 1 2
$OpTx$BIN_STEP$1026741 1 2
$OpTx$BIN_STEP$1026742 1 2
$OpTx$BIN_STEP$1026743 1 2
$OpTx$BIN_STEP$1026744 1 2
$OpTx$BIN_STEP$1026745 1 2
$OpTx$BIN_STEP$1026746 1 2
$OpTx$BIN_STEP$1026747 1 2
$OpTx$BIN_STEP$1026748 1 2
$OpTx$BIN_STEP$1026749 1 2
$OpTx$BIN_STEP$1026750 1 2
$OpTx$BIN_STEP$1026753 2 2
$OpTx$BIN_STEP$1026754 1 2
$OpTx$BIN_STEP$1026763 1 2
$OpTx$BIN_STEP$1026764 1 2
Signal Total Total User
Name Pts Inps Assignment
$OpTx$BIN_STEP$1026772 1 2
$OpTx$BIN_STEP$1026781 1 2
$OpTx$BIN_STEP$1026782 1 2
$OpTx$BIN_STEP$1026783 1 2
$OpTx$BIN_STEP$1026786 1 2
$OpTx$BIN_STEP$1026787 1 2
$OpTx$FX_DC$1026257 1 2
$OpTx$FX_DC$1026261 1 2
$OpTx$FX_DC$1026264 1 2
$OpTx$FX_DC$1026267 1 2
$OpTx$FX_DC$1026268 1 2
$OpTx$FX_DC$1026271 1 2
$OpTx$FX_DC$1026273 1 2
$OpTx$FX_DC$1026275 1 2
$OpTx$FX_DC$1026277 1 2
$OpTx$FX_DC$1026278 1 2
$OpTx$FX_DC$1026280 1 2
$OpTx$FX_DC$1026282 1 2
$OpTx$FX_DC$1026287 1 2
$OpTx$FX_DC$1026293 1 2
$OpTx$FX_DC$1026294 1 2
$OpTx$FX_DC$1026295 1 2
$OpTx$FX_DC$1026296 1 2
$OpTx$FX_DC$1026297 1 2
$OpTx$FX_DC$1026298 1 2
$OpTx$FX_DC$1026299 1 2
$OpTx$FX_DC$1026301 1 2
$OpTx$FX_DC$1026302 1 2
$OpTx$FX_DC$1026303 1 2
$OpTx$FX_DC$1026304 1 2
$OpTx$FX_DC$1026306 1 2
$OpTx$FX_SC$1026258 1 2
$OpTx$FX_SC$1026260 1 2
$OpTx$FX_SC$1026283 1 2
$OpTx$FX_SC$1026284 1 2
AS_RESYNC<0> 2 2
AS_RESYNC<1> 3 3
ATA/ASDLY 3 3
ATA/ASDLY2 3 3
ATA/ide_access_and0002/ATA/ide_access_and0002_D2 1 2
Signal Total Total User
Name Pts Inps Assignment
BG_DELAY 2 3
BUF_ATA/ASDLY 1 2
BUF_M6800BUS/Q<1> 1 2
BUF_RAMOE_OBUF 1 2
BUF_SDRAM/BCOUNT<0> 1 2
BUF_SDRAM/INIT/COUNTER<1> 1 2
BUF_SDRAM/command<0> 1 2
BUF_SDRAM/cycle_type 1 2
BUF_SDRAM/init_command<0> 1 2
BUF_SDRAM/init_command<1> 1 2
BUF_SDRAM/ready 1 2
BUSEN_INTREQR_and0001/BUSEN_INTREQR_and0001_D2 1 2
BUSEN_IRQ 3 4
BUSEN_IRQ/BUSEN_IRQ_SETF 1 2
CLK7M 1 1
CLOCKS/CLK7M_D<0> 1 2
CLOCKS/CLK7M_D<1> 1 1
CLOCKS/CLK7M_D<2> 1 1
CLOCKS/CLK7M_D<3> 1 1
CLOCKS/CLK7M_D<4> 1 1
CLOCKS/CLK7M_D<5> 1 1
CLOCKS/SPEED_D 1 1
CPCS_INT 3 4
DSACK1_SYNC 3 4
DTACK_D 1 2
DTACK_IDE 3 3
DTACK_RESYNC<0> 2 2
HIGHZ 1 1
M6800BUS/Q<0> 1 1
M6800BUS/Q<1> 2 2
M6800BUS/Q<2> 2 3
M6800BUS/Q<3> 2 3
M6800BUS/Q_Madd__add0000__and0000/M6800BUS/Q_Madd__add0000__and0000_D2 1 2
M6800BUS/Q_Madd__add0000__and0001/M6800BUS/Q_Madd__add0000__and0001_D2 1 2
SDRAM/BCOUNT<0> 1 1
SDRAM/BCOUNT<1> 1 2
SDRAM/BCOUNT_and0000/SDRAM/BCOUNT_and0000_D2 1 2
SDRAM/BURSTING 2 4
SDRAM/BURSTING/SDRAM/BURSTING_CE 1 2
SDRAM/INIT/AUTO_REFRESH/SDRAM/INIT/AUTO_REFRESH_D2 1 2
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