REV 3 - REV 5 - The beginning (ST536)

[Badwolf]

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reg [7:0] data;

Ach! That always gets me too. :)

BW

[exxos]

This should be:

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reg [7:0] data;

I wondered that but it just throws up loads more errors all over the place :shrug:

Saying that, its doing something else since doing @Badwolf's suggestions.

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ERROR:Xst:899 - "rtl/main_top.v" line 506: The logic for <data> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.
WARNING:Xst:1464 - "rtl/main_top.v" line 125: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
WARNING:Xst:1464 - "rtl/main_top.v" line 126: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
   

[exxos]

@Badwolf seems to error on your line now ?

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ERROR:Xst:899 - "rtl/main_top.v" line 506: The logic for <data> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

[Badwolf]

Progress at least -- it's down to one error.

Basically it doesn't like your always statement. You've not covered all cases I expect.

Put in an else where you just set data to D?

BW

[ijor]

always @(posedge CLK100M, negedge AS30) begin
...

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ERROR:Xst:899 - "rtl/main_top.v" line 506: The logic for <data> does not match a known FF or Latch template. The description style you are using to describe a register or latch is not supported in the current software release.

You are declaring a flip flop with an async reset (or preset), but you are not using it. The compiler gets confused and doesn't know which one is the clock and which one is the async.

[exxos]

Progress at least -- it's down to one error.

Basically it doesn't like your always statement. You've not covered all cases I expect.

Put in an else where you just set data to D?

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always @(posedge CLK100M, negedge AS30) begin

        if (BUSEN_IRQ == 1'b1) begin
          //  data[7:0] <= D[7:0];
           // data[5] <= 1'b0; //patch bit 5
			  data[7:0] <= { D[7:6], 1'b0, D[4:0] };
			  end 
			  
			  if (BUSEN_IRQ == 1'b0) begin
			  D[7:0]  <= BUSEN_IRQ ? 8'bzzzzzzzz : data[7:0];
			  end 
end

Still not happy :( Its pointing to the second to last END :shrug:

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ERROR:HDLCompilers:247 - "rtl/main_top.v" line 510 Reference to vector wire 'D' is not a legal reg or variable lvalue
ERROR:HDLCompilers:106 - "rtl/main_top.v" line 510 Illegal left hand side of nonblocking assignment

[exxos]

You are declaring a flip flop with an async reset (or preset), but you are not using it. The compiler gets confused and doesn't know which one is the clock and which one is the async.

ahhhhh.. I'm confused nevermind the compiler :lol:

It compiled now! As to if the code does what I want is another matter...

EDIT:

Nope, not booting at all now :lol: Will look at it again tomorrow when I get home from work.

[ijor]

You're assigning D[7:0] twice. Once at the top, once at the bottom. Drop the top one.

ah yep. Made no odds though.

Assigning multiple times is usually beginning because, depending on the case the language does allow it. But you should be careful and normally avoid it, because it might be confusing. In some cases (not really here) it might be useful.

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reg [7:0] data;

Ach! That always gets me too. :)

Not just you, but all of us that are used to "C" style arrays :)

[exxos]

ahhh I had a incorrect inversion. Now we booting again! Autoboot still works! Hopefully that will all function how it should with the other bits as well.
So thanks @Badwolf and @ijor for your input! :cheers:

EDIT:

:lol:

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[exxos]

So first "bug".. :lol: :roll:

When I do a "keyboard reset" the IDE can't autoboot. but if I press the reset button , it autoboots every time.. odd.