REV 3 - REV 5 - The beginning (ST536)

[exxos]

ahh FFS. :headbang:

So I did this earlier:

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localparam PATCH_ADDRESS = 30'hffFFFA01; // resets after logo
wire BUSEN_INTREQR = (A[29:0] != PATCH_ADDRESS) | AS30 | ~RW30   ; //| ~IDEINT

Then dismissed that code.. I did not put the IDEINT back in as I was only testing in STOS before.. So likely why it was resetting constantly :roll:

Now it just autobooted!!

So my initial code wasn't doing what I thought it was doing :roll: Question is, do I decode both addresses now or just the 32bit one ?

[exxos]

So next problem, how the heck to program the proper patch in verilog :shrug:

The compiler is moaning about

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assign D[7:0]  = BUSEN_IRQ ? 8'bzzzzzzzz : data;

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ERROR:HDLCompilers:73 - "rtl/main_top.v" line 551 Illegal operand of conditional operator '?:'
ERROR:HDLCompilers:185 - "rtl/main_top.v" line 551 Illegal right hand side of continuous assign
ERROR:HDLCompilers:106 - "rtl/main_top.v" line 560 Illegal left hand side of nonblocking assignment

My patch code is now this.

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reg data[7:0] ;
wire BUSEN_IRQ;
localparam PATCH_ADDRESS = 30'hffFFFA01; 
wire BUSEN_INTREQR = (A[29:0] != PATCH_ADDRESS) | AS30 | ~RW30  | ~IDEINT ; //
assign D[7:0]  = BUSEN_IRQ ? 8'bzzzzzzzz : data;
FDCP FF_IRQ( .D( BUSEN_INTREQR ), .C( CLK7M ), .PRE( 1'b0 ), .CLR( 1'b0 ), .Q(BUSEN_IRQ ) );

always @(posedge CLK100M, negedge AS30) begin
        if (BUSEN_IRQ == 1'b0) begin
            data <= D[7:0];
            data[5] <= 1'b0; //patch bit 5
        end
end

The idea being that the databus is always copied into "data" register. Then if we hit the patch address, it will have a single CLK7 delay, then the output of the FF_IRQ will go low. That's switch then enables the bus isolators.Next up when bus isolator ( BUSEN_IRQ ) Is low, it then copies the data registers back to the actual Databus and flips bit 5.

Not really sure how to tri-state the databus only when BUSEN_IRQ is enabled. But that is the line it is complaining about..

Can anyone tell me if the code even looks like it will do what it is supposed to do ?? :lol: #n00b #dumbass #clueless.

[Badwolf]

Can't immediately see what's wrong. I was looking for mismatched parenthesis or something.

Is it that BUSEN_IRQ is never set? Is it meant to be BUSEN_INTREQR?

BW

[exxos]

Can't immediately see what's wrong. I was looking for mismatched parenthesis or something.

Is it that BUSEN_IRQ is never set? Is it meant to be BUSEN_INTREQR?

BUSEN_INTREQR is just clocked via this FF, then becomes BUSEN_IRQ.

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FDCP FF_IRQ( .D( BUSEN_INTREQR ), .C( CLK7M ), .PRE( 1'b0 ), .CLR( 1'b0 ), .Q(BUSEN_IRQ ) );

I do that to give the databus chance to copy to the register (using CLK100) before isolating the bus buffers.

[Badwolf]

BUSEN_INTREQR is just clocked via this FF, then becomes BUSEN_IRQ.

Ah, yes, sorry -- ignore me.

BW

[exxos]

I think the IF part was a bit wrong..

Needs to copy and set the values when BUSEN_IRQ is HI not low. Else it be trying to get and set at the same time.

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//copy databus to registers
        if (BUSEN_IRQ == 1'b1) begin
            data <= D[7:0];
            data[5] <= 1'b0; //patch bit 5
        end

[exxos]

A tweaked version and just different errors now :(

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assign D[7:0] = {7{1'bz}};
reg data[7:0];
wire BUSEN_IRQ;
localparam PATCH_ADDRESS = 30'hffFFFA01; 
wire BUSEN_INTREQR = (A[29:0] != PATCH_ADDRESS) | AS30 | ~RW30  | ~IDEINT ; //
FDCP FF_IRQ( .D( BUSEN_INTREQR ), .C( CLK7M ), .PRE( 1'b0 ), .CLR( 1'b0 ), .Q(BUSEN_IRQ ) );

always @(posedge CLK100M, negedge AS30) begin
        if (BUSEN_IRQ == 1'b1) begin
            data[7:0] <= D[7:0];
            data[5] <= 1'b0; //patch bit 5
        end
end
assign D[7:0]  = BUSEN_IRQ ? 8'bzzzzzzzz : data[7:0];

Capture.PNG

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ERROR:HDLCompilers:108 - "rtl/main_top.v" line 509 Part-select of scalar reg array 'data' is illegal
ERROR:HDLCompilers:185 - "rtl/main_top.v" line 509 Illegal right hand side of continuous assign
ERROR:HDLCompilers:108 - "rtl/main_top.v" line 504 Part-select of scalar reg array 'data' is illegal
ERROR:HDLCompilers:106 - "rtl/main_top.v" line 504 Illegal left hand side of nonblocking assignment

[Badwolf]

You're assigning D[7:0] twice. Once at the top, once at the bottom. Drop the top one.

Also, maybe try rewriting lines 504+5 as:-

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            data[7:0] <= { D[7:6], 1'b0, D[4:0] };

?

BW

[ijor]

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reg data[7:0];

This should be:

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reg [7:0] data;

Verilog packed vs unpacked arrays:
https://www.asic-world.com/systemverilo ... pes10.html

[exxos]

You're assigning D[7:0] twice. Once at the top, once at the bottom. Drop the top one.

ah yep. Made no odds though.

Also, maybe try rewriting lines 504+5 as:-

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            data[7:0] <= { D[7:6], 1'b0, D[4:0] };

OK will do that.