So fast ROM only made it to pass 7 last night
I think part of the problem is to RAM address is muxed already and seems 10ns delay there. I've latched the address bus and added a extra clocked delay to the ram access.. it helps a lot but still not stable.
I don't really understand how it could ever work really. The address on the SDRAM likely takes 10ns to settle after /AS goes low.. So no way the SDRAM is going to latch a proper address. Hence the need for adding a delay .
I did try adding a second delay but didn't help. So there must be another problem somewhere..
Problem is as well, The CPU clock switching is done on the raw ram decode for some reason. Technically it could glitch. But also me adding in a ROM decode clause could have upset that also. It if use /AS as a clause in the ram decode line it crashes or doesn't even try to boot. So I think something is still iffy with address decoding somehow.
I tried to find way to speed up the address bus to ram, but it seems it has some initial values sent for setup and then muxed to the address bus,which seems to be where the 10ns delay comes from.
I'll have to experiment with some more delays later. I think it's just inevitable at this point the SDRAM speed is just going to have to take a small speed hit to make sure it's stable on everyone's machines. I think the fast ROM logic is just highlighting existing faults in the SDRAM timings.
Might as well fit the V1 STE booster at that point I guess 
