REV 3 - REV 5 - The beginning (ST536)

[exxos]

@Badwolf just to sanity check NVDI is running from altram ?

Its odd blitting has such a huge drop. I wonder if the caches are having a lot of hits when using fastrom , but when maprom is in play, its not having the same cache hits ( due to MMU overhead lookups) and the whole lot of tests runs slower. So when you use STRAM caches, it brings it back up again.

Might be worth just trying medium res 4 colour and see if things improve ?

[Badwolf]

So probably best sticking to MAPROM so we all testing the same setup. NVDI is adding a layer of issues , plus the blitter :lol:

Unfortunately, under TOS4, NVDI is a requirement for AltRAM. Software blitting is not available in the OS.

I assume your using PRGFLAGS for NVDI ?
...
@Badwolf just to sanity check NVDI is running from altram ?

Good question, actually. No, I haven't interfered with NVDI.PRG & don't know what the default is. Will check this later.

I suppose I ought to solder on my Flash and test with EmuTOS in ROM.

Not having software blitting in TOS4 is a right pain. One of the things to look into when I get a chance. I think it was @shoggoth77 who said patching TOS's jumptable should be easy, but my disassembly skillz are in their infancy and my knowledge of the OS even more embryonic.

BW

[exxos]

I have been trying to inject data into the CPU but not having much luck :roll:

Code: Select all

localparam PATCH_ADDRESS = 30'h300000; 
wire BUSEN_INTREQR = (A[29:0] != PATCH_ADDRESS) | AS30 | ~RW30  ; 
assign D[5] = BUSEN_INTREQR ? 1'bz : 1'b0;

Idea is when this addresses is accessed, it will disable the databuffers on the ST536. At that point all the data bits should all be high. So when I access the address, D5 could be set to 0.

Problem is, no matter what I read or write to that address it always comes back as "238". Which makes no sense because that is %11101110.. Where 2 bits are low.

If I remove the D5 line, I can read and write all sorts of values perfectly well. So it does seem like I'm accessing the correct address. But for some reason there is something up with that third line and no idea what ?

[stephen_usher]

Well, if AS30 is true or RW30 is false then the test to set D5 will be true irrespective as to whether the address is being selected. Is that what you want?

[exxos]

Well, if AS30 is true or RW30 is false then the test to set D5 will be true irrespective as to whether the address is being selected. Is that what you want?

if AS30 is high then nothing is accessing the bus, and BUSEN_INTREQR will be high.

If writing to the address then invented, BUSEN_INTREQR will be high.

So the equation is that if the address matched, then zero, OR AS30 high, OR WRITE.

So the only way BUSEN_INTREQR can be low is when READing, and AS30 is low, and address matches (low).

D[5] = BUSEN_INTREQR = 0.

EDIT:

There isn't a true/false thing going on, this are literally wired to the CPU "as is".

[Badwolf]

Well, if AS30 is true or RW30 is false then the test to set D5 will be true irrespective as to whether the address is being selected. Is that what you want?

If (register not matched) is true OR AS30 is high OR RW30 is low the test flag is high so D5 will be high-Z. That's correct.

Pretty much all these are active low.

If I remove the D5 line, I can read and write all sorts of values perfectly well. So it does seem like I'm accessing the correct address. But for some reason there is something up with that third line and no idea what ?

What is the configuration of your other data lines? Both in the assign statements and in the declaration at the top of the module (input/inout/output etc.).

BW

[exxos]

What is the configuration of your other data lines? Both in the assign statements and in the declaration at the top of the module (input/inout/output etc.).

There are no other data lines in use anywhere in the code AFAIK. The compiler mostly moaned and removed the references.

In the top module it is just like all other TF projects...

Code: Select all

module main_top #(
           parameter CLOCK_PHASE=7)
       (

           input			RESET,

           // all clock lines.
           input   			CLK7M_RAW,
           input   			CLK100M,
           output   		CLKCPU,
           output  			CLKRAM,

           input [29:0]    	A,
           inout [15:0]   	D,

           //  SDRAM Control
           output			CLKRAME,
           output [12:0]    ARAM,
           output [1:0] 	BA,
           output			CAS,
           output [3:0] 	DQM,
           output			RAMWE,
           output			RAS,
           output			RAMCS,
           output			RAMOE, 
           etc

It does moan about D5 as well, not sure if is a bad thing or not..

Code: Select all

WARNING:Xst:1464 - "rtl/main_top.v" line 206: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
WARNING:Xst:1464 - "rtl/main_top.v" line 207: Exactly equal expression will be synthesized as an equal expression, simulation mismatch is possible.
WARNING:Xst:646 - Signal <CLK7M_D<7>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:647 - Input <WAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <A<15:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <A<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1305 - Output <WAIT> is never assigned. Tied to value 0.
WARNING:Xst:647 - Input <A<29:26>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:646 - Signal <init_clke> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <WAITSTATE> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:2565 - Inout <D<11>> is never assigned.
WARNING:Xst:2565 - Inout <D<12>> is never assigned.
WARNING:Xst:2565 - Inout <D<13>> is never assigned.
WARNING:Xst:2565 - Inout <D<14>> is never assigned.
WARNING:Xst:2565 - Inout <D<15>> is never assigned.
WARNING:Xst:2565 - Inout <D<3>> is never assigned.
WARNING:Xst:2565 - Inout <D<4>> is never assigned.
WARNING:Xst:2565 - Inout <D<5>> is never assigned.
WARNING:Xst:2565 - Inout <D<6>> is never assigned.
WARNING:Xst:647 - Input <IDEWAIT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2565 - Inout <D<7>> is never assigned.
WARNING:Xst:2565 - Inout <D<8>> is never assigned.
WARNING:Xst:2565 - Inout <D<9>> is never assigned.
WARNING:Xst:647 - Input <IDEINT> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:1306 - Output <INT2> is never assigned.
WARNING:Xst:2565 - Inout <D<10>> is never assigned.
WARNING:Xst:1780 - Signal <rd6> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd5> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd4> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd3> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd2> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd1> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <rd> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <dtack_delay9> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <WAIT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <SD8> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:653 - Signal <PUNT_INT> is used but never assigned. This sourceless signal will be automatically connected to value 1.
WARNING:Xst:646 - Signal <PUNT_COMB> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <DTACK_RESYNC<1>> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:1780 - Signal <BUSEN_D> is never used or assigned. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:646 - Signal <BGACK_INT> is assigned but never used. This unconnected signal will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <CLK7M_D_7> of sequential type is unconnected in block <clocks>.
WARNING:Xst:1293 - FF/Latch <command_3> has a constant value of 0 in block <sdram>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:2677 - Node <DTACK_RESYNC_1> of sequential type is unconnected in block <main_top>.
WARNING:Xst:2677 - Node <CLK50M> of sequential type is unconnected in block <CLOCKS>.
WARNING:Xst:2677 - Node <CMD_3> of sequential type is unconnected in block <INIT>.
WARNING:Xst:2677 - Node <CLKE> of sequential type is unconnected in block <INIT>.
WARNING:NgdBuild:470 - bidirect pad net 'D<11>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<12>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<13>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<14>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<15>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<3>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<4>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<5>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<6>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<7>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<8>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<9>' has no legal driver
WARNING:NgdBuild:470 - bidirect pad net 'D<10>' has no legal driver
WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will
   use the default filename of 'main_top.ise'.
WARNING:Cpld:936 - The output buffer 'INT2_OBUF' is missing an input and will be
   deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'D<10>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<11>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<12>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<13>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<14>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<15>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<3>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<4>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<5>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<6>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<7>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<8>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'D<9>'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'IDEINT'.  The input(s) are unused
   after optimization. Please verify functionality via simulation.

[Badwolf]

There are no other data lines in use anywhere in the code AFAIK. The compiler mostly moaned and removed the references.
In the top module it is just like all other TF projects...

Lots of complaints about no driver. Why not change to output (for simplicity) and actively drive the lot for testers?

Code: Select all

	output [15:0] D,

Code: Select all

	assign D[15:0] = BUSEN_INTREQR ? 16'bzzzzzzzzzzzzzzzz : 16'b1100110000110011; // just a test pattern. do 16'hBEEF if you like.

That will shut up a lot of the errors and nowt should now be floating.

BW

[exxos]

That will shut up a lot of the errors and nowt should now be floating.

Yep.. but now have a new problem, I am out of space with your new line :(

I tried

Code: Select all

assign D[1:0] = BUSEN_INTREQR ? 1'bzz : 1'b00;

Now its not booting :(

Seems when I do this:

Code: Select all

assign D[1:0] = BUSEN_INTREQR ? 1'bzz : 1'b00;

it does not boot.

But if I do this, it does boot.

Code: Select all

assign D[0] = BUSEN_INTREQR ? 1'bz : 1'b0;
assign D[1] = BUSEN_INTREQR ? 1'bz : 1'b0;

So no idea what is going on
:dizzy:


EDIT:

I don't think the bus isolation is working. Because I just triggered the bus isolation on the address, so whatever value is read or written to that address would always come back as all 1's.. Its coming back as is written..

Have to call it a night now anyway, need to get off the PC for a bit :(

[Badwolf]

I thought I posted this, but I can't find it now:-

Seems when I do this:

Code: Select all

assign D[1:0] = BUSEN_INTREQR ? 1'bzz : 1'b00;

it does not boot.

But if I do this, it does boot.

Code: Select all

assign D[0] = BUSEN_INTREQR ? 1'bz : 1'b0;
assign D[1] = BUSEN_INTREQR ? 1'bz : 1'b0;

So no idea what is going on

The 1 before the apostrophe is the number of bits, so in the first code you're assigning a two line wide output (D[1:0] = two wires) with a single bit (1'b00 means D[0] is 0 and D[1] is in an unknown state).

BW