BLITTER RE-CREATION THOUGHTS

Progress on our FPGA cores.
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Cyprian
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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian »

ijor wrote: 27 Oct 2022 21:26 Someone from Poland that it is also working on some of those ATX ST motherboards. I understand he tested it both on original hardware and an ATX motherboard.
do you remember the nickname?
I asked x_angel (ATX ST author) but he said it wasn't him
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ijor
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Re: BLITTER RE-CREATION THOUGHTS

Post by ijor »

Cyprian wrote: 28 Oct 2022 09:04 do you remember the nickname? I asked x_angel (ATX ST author) but he said it wasn't him
It is not x_angel. Well, at least, I think it is not him. I'm not sure about the nickname, but even if I knew it, I don't think it would be correct to post here personal details about a private email exchange. Honestly, I don't even know if his work is public or not.
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

@Cyprian Going back to these tests viewtopic.php?p=51449#p51449

These 2 images were original and our blitter. What exactly is "out" on our core ? Looks like some timing is slightly to fast to slightly to slow causing some odd screw in the test ?

Original in STFM - program 1.jpeg
Sparkalaphobia in STFM - program 1.jpeg
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Cyprian
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Re: BLITTER RE-CREATION THOUGHTS

Post by Cyprian »

@exxos I see that the second the BLiTTER pass starts 4 cycles earlier, but it could be a result of miscounting the bus cycles in the first pass.
Sparkalaphobia on the right side, upper arrow - the first the BLiTTER pass , the bottom arrow - the second pass:

20221029_sparklaphobia.png

May I ask you to do one more test? It provides some additional details like, when the BLiTTER touches the bus ( black/blue/green strips) and how it interacts with a long the CPU instructions like "DIWS.W" (white spaces between each the BLiTTER pass)

BLiT_H6a4h.png
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ATW800/2 / V4sa / Lynx I / Mega ST 1 / 7800 / Portfolio / Lynx II / Jaguar / TT030 / Mega STe / 800 XL / 1040 STe / Falcon030 / 65 XE / 520 STm / SM124 / SC1435
DDD HDD / AT Speed C16 / TF536 / SDrive / PAK68/3 / Lynx Multi Card / LDW Super 2000 / XCA12 / SkunkBoard / CosmosEx / SatanDisk / UltraSatan / USB Floppy Drive Emulator / Eiffel / SIO2PC / Crazy Dots / PAM Net
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Cyprian wrote: 29 Oct 2022 09:15 May I ask you to do one more test? It provides some additional details like, when the BLiTTER touches the bus ( black/blue/green strips) and how it interacts with a long the CPU instructions like "DIWS.W" (white spaces between each the BLiTTER pass)
They were done in this thread viewtopic.php?p=51449#p51449

So if our glitter is taking the bus too fast, it doesn't make sense why our glitter is slower than the original.
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Icky
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Re: BLITTER RE-CREATION THOUGHTS

Post by Icky »

We, @ijor and I, have a bit of an update on the Phoenix Sparkalaphobia aka the Hardware FPGA Blitter with Ijor's Blitter core. We have been working in the background on the core and testing. Ijor has been instrumental in helping get the timings and plumbing in place. I have learnt a great deal more about FPGAs through this experience.

We have performed extensive testing and are now confident to announce we have a working Blitter core on real hardware that matches the original Blitter.

:cheer: :cheer: :cheer:

Now for the details

Our tests have been on the following hardware: an original STFM and Phoenix H5 motherboard and we have tested on TOS102 and TOS104.

The software we used:
Using the above software we got matches of all the patterns from Cyprian's programs both original and FPGA version matched exactly. Ijor's delay test program gave the same results as an original Blitter on an STFM and H5.

However the GEMBench tests spawned tangential discussions with @exxos and Ijor on GEMBench timing (rounding errors). We were seeing a 0.005 difference in running on TOS102 which is negligible but GEMBench rounding was causing 99% score. That said GEMBench scores on TOS104 are 100% between original and FPGA.

Below are some example results. You may also notice that there are timing differences between TOS102 and TOS104 - Ijor mentioned in the thread Blitter on H5 Test the Blitter code section is similar in TOS104 - TOS206 but different in TOS102. There is also more discussion in that thread about the GEMBench timings.
  • Original STFM with original Blitter on TOS102 the Blitter timing is 3.570
  • Original STFM with Sparkalaphobia Blitter on TOS102 the Blitter timing is 3.575
  • Original STFM with original Blitter on TOS104 the Blitter timing is 3.590
  • Original STFM with Sparkalaphobia Blitter on TOS104 the Blitter timing is 3.590
What next?

Well with the shortage of FPGAs currently there won't be many Sparkalaphobia boards being made other than a few DEV ones for continued testing etc. However we now have a solution for a future Blitter chip replacement for original and Phoenix motherboards.
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

Congratulations @Icky and @ijor :thumbup:

Give yourselves a pat on the back. We don't have one of those icons, so this will have to do.. :chairsmack: :lol:
EvilFranky
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Re: BLITTER RE-CREATION THOUGHTS

Post by EvilFranky »

Great news!

What's planned for added features? ;)
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exxos
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Re: BLITTER RE-CREATION THOUGHTS

Post by exxos »

EvilFranky wrote: 23 Dec 2022 21:10 What's planned for added features? ;)
32MHz ;)
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Re: BLITTER RE-CREATION THOUGHTS

Post by EvilFranky »

exxos wrote: 23 Dec 2022 21:20
EvilFranky wrote: 23 Dec 2022 21:10 What's planned for added features? ;)
32MHz ;)
:D :D :D

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