DFB1 FPU experiment thread

[frank.lukas]

I haven't read all the posts but I read something that the PAK has waitstates (I mean two) for the FPU added? don't know if that's right? The PAK has no problem run the FPU with the same Clock as the CPU do. Max 50Mhz ...

The Atari TT has no problem with the FPU too.

[foft]

I haven't read all the posts but I read something that the PAK has waitstates (I mean two) for the FPU added? don't know if that's right? The PAK has no problem run the FPU with the same Clock as the CPU do. Max 50Mhz ...

The Atari TT has no problem with the FPU too.

Do you mean 2 extra cycles after after the FPU drops DSACK? What is the PAK?

I tried the extra two capacitors and the 3rd board isn't running the FPU with a 40MHz crystal with either the official CLK/2 firmware or my CLK=CLK firmware. It does work with option 2 on though.

[frank.lukas]

PAK68/3 ...
https://www.wrsonline.de/atari_index.html

... use the Google Translator.

[foft]

Thanks. Schematics are on this pdf: http://www.s100computers.com/N8VEM_Arch ... 8B2BTm.pdf

[Badwolf]

I find this bit interesting:-

_{(Googled to English)}

FPU fix
Eliminates the FPU errors (11 bombs), which could occasionally occur with frequent FPU accesses from within the ST-RAM. With this GAL, the 245s on the PuPla/1 are switched off at the earliest possible time during read access, so subsequent FPU access remains undisturbed. Positive side effect: If you want to operate a 68000 on the PAH, you previously needed a flying connection from the jumper J5 Pin 1 on the PAK to pin 5 of the GAL on the PuPla/1. This is no longer necessary.
Necessary patch: Flying connection from the PAH to the PuPla/1 necessary: From the GAL U1 Pin 20 (on the PAH) via a resistance 68 ohms (tight to U1) to pin 5 of this GAL on the PuPla/1. If there (pin 5 of the GAL) there was previously a line to J5 on the PAK, it can be removed again.
Note: This GAL works with FPU fix turned on even if no FPU is used on the PAK at all (disabled or not available at all via jumper).

This implies problems with STRAM 'stepping on the toes' of the FPU's databus, I think. Perhaps delaying FPUCS for an unrealistic number of cycles to see if chips that previously won't run now can, or chips than can run can now run faster would be a worthwhile test.

DFB1 intentionally doesn't have 245 buffers to the motherboard to reduce the part count so the extra capacitance that causes, or any slow bus releases could become an issue.

BW

[foft]

Along these lines I thought it’d be interesting to test the dfb1 standalone, without the falcon. ie if we power it and write a custom rom with the fputest. A far shorter simpler databus. Perhaps we have some echos on the address and data lines.

My other thought is to wire up an fpga as a 68030 to see what it sees in its internal logic analyser. Of course it doesn’t need to be a cpu just do some fpu access bus cycles.

At the moment I feel blind to what is going on on the address and data bus. I can’t really capture them all on my 8 channel logic analyser!

[foft]

I've not done any of the trickier stuff yet ...

However I found a few mins to swap some CPUs and FPUs.

I left the board that works with 40/40 alone.

For the other two boards. Both have official release firmware, both with 40MHz crystals. The FPU worked on one but not on the other.

I had 3 FPUs and 3 CPUs spare to try in these two boards. I found that the working CPU/FPU combination works on both boards. No other combination works. One FPU just seems dodgy full stop. All CPUs seem ok in general, just not with an FPU without option 2 jumpered.

So, seems no bad DFB 1s, just non-working CPU/FPU combinations.

To take this further I think I really need some test harness boards, so really down to if I can be bothered to design/make any. Might be something fun to play with this year, in the continuing absence of any low end FPGA availability yet from Intel!

[Badwolf]

Hi @foft,

Thanks for these analyses so far.

I think you're right -- there is a degree of CPU & FPU influence over the results, but it could be as simple as each one's jitter, overvoltage, ground bounce, ramp-up timing tolerance or their inherent internal capacitance or anything.

Throw into the mix that some of those CPU & FPU combinations will work well in other boards (PAK, TF534) or on a TT at speeds that they don't on the DFB1 and there is definitely a board influence.

I think extra decoupling caps on both CPU and FPU can't hurt. Experimenting with the chip select delay may be informative on marginal combinations, bodging in inline termination to the AS, DS, CS lines (as @12-MHz did) or possibly even just fitting stronger pull-ups on the address and data lines may also show some effects.

You're in a good position to do some of these given you have enough combinations of boards and working/non-working chips, but it'd be a time consuming and potentially ultimately fruitless venture, so I shan't ask you to try any of them but if you do venture into that level of boredom that building a test harness looks attractive, perhaps consider some of those first?

I have experimented with more data line pull-ups in the past, but I can't say I saw any effect on the FPU at the time.

IMG_4905.jpeg (285.31 KiB) Viewed 1933 times

BW

[markus0321]

Hi @foft,

Thanks for these analyses so far.

I think you're right -- there is a degree of CPU & FPU influence over the results, but it could be as simple as each one's jitter, overvoltage, ground bounce, ramp-up timing tolerance or their inherent internal capacitance or anything.

Throw into the mix that some of those CPU & FPU combinations will work well in other boards (PAK, TF534) or on a TT at speeds that they don't on the DFB1 and there is definitely a board influence.

I think extra decoupling caps on both CPU and FPU can't hurt. Experimenting with the chip select delay may be informative on marginal combinations, bodging in inline termination to the AS, DS, CS lines (as @12-MHz did) or possibly even just fitting stronger pull-ups on the address and data lines may also show some effects.

You're in a good position to do some of these given you have enough combinations of boards and working/non-working chips, but it'd be a time consuming and potentially ultimately fruitless venture, so I shan't ask you to try any of them but if you do venture into that level of boredom that building a test harness looks attractive, perhaps consider some of those first?

I have experimented with more data line pull-ups in the past, but I can't say I saw any effect on the FPU at the time.


IMG_4905.jpeg


BW

What is the resistance of these resistors?

[Badwolf]

What is the resistance of these resistors?

You quoted my full message where I spoke about various terminators & pull-ups. Which ones do you mean?

But also: how long's a piece of string. The value that works on your board is the right one.

BW