Ah, I may be a bit hazy.foft wrote: 07 Dec 2022 11:40 Yes that is the one I meant, I thought the CLK referenced was the CPU clock with sequential logic in the GAL. I didn't realize it was because its a clocked GAL.
I'll dig it out of the PDF later. Do you still have a failing FPU board, or are they all now working?
Absolutely no difference to the speed or reliability that I found. I was worried about the latter (which is why I routed it via the CPLD in the first place), but if I were designing DFB2 with an FPU, I'd probably drop that and have a tri-state DSACK[x] line.So with the DSACK bodge wires did it make any difference to how fast you could run the FPU?I've tried both (see previous picture with DSACK bodge wires and tristate DSACK[x] driver from the CPLC), but since I planned to run the FPU more slowly than the CPU I figured this would be a prudent modification to the logic to stop the FPU stomping on any following non-FPU cycle.
I'm not keen to make modifications like that to a potential rev6 board -- I don't want to bring incompatible firmwares into the mix too -- although I'd be happy to add more/redesign the layout of the capacitors. Perhaps switch to an SMD socket (has the advantage you can solder the FPU directly on then). That kind of thing.
I could do the pin assignment on the CPLD better as well -- I wasted CLK pins on outputs in the (incorrect) belief that since these were the clocks upon which everything else cued, they should be the global ones. Sadly it doesn't work like that.
That said, if I did do a DFB2, it might drop the FPU entirely as since Anders has provided a soft FPU now and there is always the possiblity to use the onboard FPU (with one fly wire to a GAL's leg), I'm thinking they're more trouble than they're worth.
BW

