exxos's DFB1 trials

Discussion and support for the DSTB1 & DFB1 boosters by BadWolf..
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Re: exxos's DFB1 trials

Post by Badwolf »

foft wrote: 07 Dec 2022 11:40 Yes that is the one I meant, I thought the CLK referenced was the CPU clock with sequential logic in the GAL. I didn't realize it was because its a clocked GAL.
Ah, I may be a bit hazy.

I'll dig it out of the PDF later. Do you still have a failing FPU board, or are they all now working?
I've tried both (see previous picture with DSACK bodge wires and tristate DSACK[x] driver from the CPLC), but since I planned to run the FPU more slowly than the CPU I figured this would be a prudent modification to the logic to stop the FPU stomping on any following non-FPU cycle.
So with the DSACK bodge wires did it make any difference to how fast you could run the FPU?
Absolutely no difference to the speed or reliability that I found. I was worried about the latter (which is why I routed it via the CPLD in the first place), but if I were designing DFB2 with an FPU, I'd probably drop that and have a tri-state DSACK[x] line.

I'm not keen to make modifications like that to a potential rev6 board -- I don't want to bring incompatible firmwares into the mix too -- although I'd be happy to add more/redesign the layout of the capacitors. Perhaps switch to an SMD socket (has the advantage you can solder the FPU directly on then). That kind of thing.

I could do the pin assignment on the CPLD better as well -- I wasted CLK pins on outputs in the (incorrect) belief that since these were the clocks upon which everything else cued, they should be the global ones. Sadly it doesn't work like that.

That said, if I did do a DFB2, it might drop the FPU entirely as since Anders has provided a soft FPU now and there is always the possiblity to use the onboard FPU (with one fly wire to a GAL's leg), I'm thinking they're more trouble than they're worth.

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Re: exxos's DFB1 trials

Post by foft »

Badwolf wrote: 07 Dec 2022 12:03
foft wrote: 07 Dec 2022 11:40 Yes that is the one I meant, I thought the CLK referenced was the CPU clock with sequential logic in the GAL. I didn't realize it was because its a clocked GAL.
Ah, I may be a bit hazy.

I'll dig it out of the PDF later. Do you still have a failing FPU board, or are they all now working?
I have 3 boards and they all work properly except the FPU.

So far I added the extra two FPU capacitors on only one of them. Also I only put eprom on one of them so far too, though I just receive the chips so will add them later this week.
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Re: exxos's DFB1 trials

Post by Badwolf »

foft wrote: 07 Dec 2022 12:07 I have 3 boards and they all work properly except the FPU.

So far I added the extra two FPU capacitors on only one of them. Also I only put eprom on one of them so far too, though I just receive the chips so will add them later this week.
Oh, that's good -- I thought you'd fixed them by throwing CPLDs at the problem until they started working. If you got a few sample units misbehaving we could try a few things.

Do you fancy a bit of firmware/bodge wire experimentation? We can open up a new thread to track things, if so.

We could try playing with the FPUCS line, like you suggested.

Move on to removing the FPU dependency from the FPU_DSACK array.

Finally the bodge wire (tristate DSACK) one isn't too much work either on firmware or with the soldering iron.

Even removing R18, wiring the two CLK pins together then driving the whole lot at 25MHz is an option.

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Re: exxos's DFB1 trials

Post by foft »

That would be great. I'll set up a thread. Thanks!
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Re: exxos's DFB1 trials

Post by exxos »

I am dead in the water with this until I can find a replacement 288 PLD. Does anyone have any source for these at all ?

EDIT:

Looks like UTsource have "new" but who knows. To have any hope of getting them this year it have to be from them and pay the courier price as well :roll:

EDIT2:

Screw it, ordered 10.
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Re: exxos's DFB1 trials

Post by exxos »

I still unfortunately have not had time to test the PLD's out :(

But I have come to a basic agreement with badwolf allowing me to make the changes I want to do to the board and producing next revision at some point. It is also why I've been trying to get kicad installed on the Linux laptop for a while now. I am not very familiar with it all at all, so it could take some time to figure out. Progress will unfortunately be slow because I cannot do more than about half an hour work a day on the PC these days :( though I am also looking into ways of speeding things up with the help of third parties.So there may be some sporadic updates very soon.
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Re: exxos's DFB1 trials

Post by exxos »

Finally got the schematics to load properly :D

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Re: exxos's DFB1 trials

Post by exxos »

Getting the hang of it now :lol:

:fire: :hide: :fire:

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Absolutely nobody will figure out what I am doing and why :lol:
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Re: exxos's DFB1 trials

Post by alexh »

exxos wrote: 23 Apr 2023 22:40 Absolutely nobody will figure out what I am doing and why :lol:
Adding a phantom like bus accelerator? The CT60e has an integrated bus accelerator.
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Re: exxos's DFB1 trials

Post by exxos »

alexh wrote: 24 Apr 2023 10:21 Adding a phantom like bus accelerator? The CT60e has an integrated bus accelerator.
Afraid not. I was more referring to the FPU socket change.

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