REV 3 - REV 5 - The beginning (ST536)

[exxos]

Printing underway of rev5..

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[PhilC]

@exxos looking forward to building one of those.

[exxos]

@exxos looking forward to building one of those.

Will send you one when you agree that cat song is awesome!

[exxos]

Paste looked like it went on pretty well..

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Heating the board upon the paste printer.. it only goes up to 240c.. Which I don't think is necessarily a bad thing in this case as I don't want all the parts falling off the bottom of the board so had to finish the topside off with my gas soldering iron..

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The PLCC socket is not so easy to do. But I anticipated this problem when I positioned the socket.. So I have it on my hotplate that 380c now and the solder is melting on the socket now.. Thankfully does not look like the plastic is melting.. Yet...

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Soldering looks good..

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[PhilC]

I did the last rom socket with 200C hot air and the socket was fine but my solder paste is 180C melting point.

[exxos]

Built up and working I've given up with the STE. TOS206 really isn't happy on the STE.. But even with EMUTOS, it gets stuck in a odd resetting loop.. Like gets to desktop, 10 seconds resets.. It also looks like EMUTOS doesn't like my EC CPU either as I went back to my H4 and had odd issues as well until I put the full 030 back in.

Annoyingly, I still seem to be limited to 16MB so no idea what's going on there still.

[PhilC]

Great news it all works straight away. Maybe try the STe once everything else is up and running 100%

[Badwolf]

Annoyingly, I still seem to be limited to 16MB so no idea what's going on there still.

16MB is to my mind suspiciously like only one bank is working (with 2x256Mbit chips there are four banks, each contributing 16MB).

One easy thing you could try to prove it's not related to that is to move where the bank select comes in the address translation.

You'll find some lines in the sdram controller verilog file that look like this:-

Code: Select all

address <= { A[24:12] };
command <= CMD_ACTIVE;
bank <= A[26:25];

So, the bank selection corresponds to address lines 25 and 26.

They read 01 for the first 16MB of TT-RAM, 10 for the second 16MB, 11 for the third and 00 for the fourth.

The easy test of those lines, therefore is to position them at a different part of the memory map, eg:

Code: Select all

address <= A[26:14];
command <= CMD_ACTIVE;
bank <= A[13:12];

Now the banks are interleaved throughout the address space, switching every 4k.

If you're still restricted to 16MB, you've proved it's not the obvious & I'd start checking your bus error logic. If you get none (well technically 4k, but I don't think anything will detect that!), you've probably found the culprit.

BW

[exxos]

@Badwolf Its odd as it ticks over address 1F but then fails at the same address range later., can't check until I get home, but was like 1F0006a28 or something odd like that.

Both my boards have the same fault. I need to check the ram decode address line again, but think it's decoding the full 64MB. Even so, it doesn't make sense that lower addresses work up to 1F then fail on lower addresses.

[Badwolf]

@Badwolf Its odd as it ticks over address 1F but then fails at the same address range later., can't check until I get home, but was like 1F0006a28 or something odd like that.

Both my boards have the same fault. I need to check the ram decode address line again, but think it's decoding the full 64MB. Even so, it doesn't make sense that lower addresses work up to 1F then fail on lower addresses.

So it doesn't quite make it to 16MB?

Does it exhibit the same issues 16MB higher? Eg. if you test from 02000000 to 03000000 is it clear, up to the 2F range?

I did have some similar issues when I was debugging my clock timings. Lower address ranges in a bank were fine, but the higher ones would tend to fail. Your board has 50MHz for the CPU and 100MHz for the RAM, as I understand it. How 'in sync' are they on the 'scope?

BW