exxos's DFB1 trials

[exxos]

That's not a trace, that's the oscilloscope monster's fangs!

It seems the does that when it crashes. I do see some relative good clock switching when it is running but difficult to capture. But even so I don't know why that would happen at 50MHz anyway. Should be pretty much a passthrough from the oscillator ?

[Badwolf]

It seems the does that when it crashes. I do see some relative good clock switching when it is running but difficult to capture. But even so I don't know why that would happen at 50MHz anyway. Should be pretty much a passthrough from the oscillator ?

Wait, that's the CPUCLK output line?

You need to get the CLKOSC input line on the second channel, then. It looks like it's trying to produce a 66% duty wave.
BW

[exxos]

Wait, that's the CPUCLK output line?

Yep.

You need to get the CLKOSC input line on the second channel, then. It looks like it's trying to produce a 66% duty wave.
BW

But it only does that when it crashes.. It looks fine when it is switching between 16Mhz / 50MHz otherwise.

I'm currently trying to figure out why locks up at 50MHz in the first place.

[exxos]

The plot thickens once again

IMG_0262.JPG (218.05 KiB) Viewed 1369 times

IMG_0263.JPG (265.13 KiB) Viewed 1369 times

[Badwolf]

I think you're only seeing it when it crashes as when it crashes it presumably ends with no bus cycle happening, so switches up full-time to 50MHz.

The obvious thing to question is whether CLKOSC input is actually getting down to 0V now or if it's floating up & therefore we're not getting a symmetrical signal.

The plot thickens once again

The top one looks relatively normal (other than the slow cycle is on the low branch -- I must have inverted it from DSTB1). The bottom one is starting to see that 66% duty cycle appaering again.

What does the input look like as this is happening?

[exxos]

What does the input look like as this is happening?

What input are you referring to ? The oscillator ? that is fine..

[Badwolf]

What does the input look like as this is happening?

What input are you referring to ? The oscillator ? that is fine..

The CPLD-side of the oscillator's TUNE resistor.



Between the 33 and the PLD.

There's a schmitt trigger on the PLD's clock input, so any input oscillator floating away from ground at the bottom of its duty would produce a skewed duty cycle internally.

BW

[dml]

Can the oscillator be ac-coupled through a small cap before the 33R resistors? Not sure what is normally done here but does suggest there is some kind of dc offset there?

[EDIT]

Actually any ac-coupling cap would need to be after those other caps, as those can charge up to a dc offset.

[EDIT]

On seconds thoughts, no that's rubbish - they won't average a DC offset if has been taken out beforehand. Pff.

[exxos]

Between the 33 and the PLD.

Looks the same both sides of the resistor.

Something else has gone wonky somewhere either there has been a bad connection develop or something else is broken because it seemed to be running at 50x less speed just.. The clock is still switching away.. Bizarre..

[exxos]

Oh after about 10 minutes it did the first dash on TOS's boot up RAM test