ST536 STE EDITION

[exxos]

That might explain things but you still need a for good measure. I've got my last 4 here

Yeah.. its hard to keep up and remember everything

Now I wonder what buffers @coonsgm has on his...

[PhilC]

p.s. can you send me the stl file for the cpu spacer, I melted this one

[exxos]

Some "notes" comparing the 144 10ns to a 288 6ns with piping..

Signal	XC95144XL-10 (ns)	XC95288XL-6 (ns)	Difference (ns)	Notes
ARAM<0>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<1>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<2>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<3>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<4>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<5>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<6>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<7>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<8>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<9>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<10>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<11>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
ARAM<12>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
AS	14.5	9.2	-5.3	High-Z control, faster grade
AVEC	13.7	7.6	-6.1	Logic optimized, faster grade
BA<0>	14.5	3.8	-10.7	Pipelined, constrained to 8 ns
BA<1>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
BERR	30.1	16.0	-14.1	Logic optimized, faster grade
BG	13.7	7.6	-6.1	Registered, faster grade
BGACK30	21.4	10.6	-10.8	Logic optimized, faster grade
CAS	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
CBACK	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
CIIN	14.5	3.8	-10.7	Pipelined, faster routing
CLKCPU	5.8	3.8	-2.0	Clock path optimized
CLKRAM	10.0	6.0	-4.0	Inverted CLK100M, faster grade
DQM<0>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
DQM<1>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
DQM<2>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
DQM<3>	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
DSACK<1>	21.4	10.6	-10.8	Logic optimized, faster grade
DTACK	22.4	13.0	-9.4	Logic optimized, faster grade
E	13.7	7.6	-6.1	Logic optimized, faster grade
IOR	13.7	7.6	-6.1	Logic optimized, faster grade
IOW	13.7	7.6	-6.1	Logic optimized, faster grade
LDS	14.5	9.2	-5.3	High-Z control, faster grade
RAMOE	5.8	3.8	-2.0	Pipelined, faster routing
RAMWE	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
RAS	13.5	3.8	-9.7	Pipelined, constrained to 8 ns
STERM	13.7	3.8	-9.9	Pipelined, faster routing
UDS	14.5	9.2	-5.3	High-Z control, faster grade
VMA	14.5	9.2	-5.3	High-Z control, faster grade

[exxos]

p.s. can you send me the stl file for the cpu spacer, I melted this one

Yep..

[PhilC]

Ok with main_top.jed. the 64mb now works in Emutos but ST536 Tos just hangs, it does the memory test, tries to load from ASCI and then hangs.

I can't get anything yet to boot from IDE

[exxos]

Ok with main_top.jed. the 64mb now works in Emutos but ST536 Tos just hangs, it does the memory test, tries to load from ASCI and then hangs.

I can't get anything yet to boot from IDE

I'm not sure at this point if TOS IDE autoboot is even enabled in that firmware.. better to try EMUTOS.. load MAPROM, leave it running YAARTTT for a hour or more..

[PhilC]

I just get a no TT ram present error when using yartTT. I'll check my soldering a bit later on and put it in the US cleaner

[exxos]

I just get a no TT ram present error when using yartTT. I'll check my soldering a bit later on and put it in the US cleaner

using EMUTOS after a cold boot (via keyboard) ? does it show 64MB on its splash ?

[PhilC]

I just get a no TT ram present error when using yartTT. I'll check my soldering a bit later on and put it in the US cleaner

using EMUTOS after a cold boot (via keyboard) ? does it show 64MB on its splash ?

Yes it does

[exxos]

The 288-6 is about $49 a pop at JLC. Waiting for a quote currently.

I also asked my sourcing company for a price for 100 of them. See if there are any better deals anywhere but that unfortunately then leads to limiting to UK assembly.. Which could actually increase costs in particular on small batches

I guess the huge stack of 144XL's I have (genuine new parts), I will list in the store at some point, as I probably won't need them now. But they be fine for original TF536 related builds anyway.

According to Grok, all the timings in the 144 are bad and to slow for the SDRAM. The 288 is much better, and piping means I can "lock" better what timings need to remain the same. Grok did all the analysis and workings out and if to be believed, it claims my new build should work fine.. But it really needs to be tested in real hardware... If it still doesn't work a huge timing analysis will have to be properly done to figure it all out.

It leaves me with a bit of conundrum, because its possible the 144 could be used and may work for some people.. But the thing is full, and clawing back a couple of registers by removing the faster ROM access (and in some cases removing the IDE AutoBoot) to gain some reg's back.. And if I do manage to save couple of registers elsewhere will likely screw up the RAM timing again anyway. It's like trying to diagnose a car engine which has a hundred loose bolts...

The larger PLD does let me add some other stuff and potentially gives me a lot of room or future firmware stuffss in the future maybe.. Currently the annoying thing is the high price of the PLD , but its just unavoidable at this point now..