TF CD32 Riser Revision 2 Design Complete

[arkadiusz.makarenko]

The solution to this is to assign one of the INTSIG wires to A5 in the CPLD.

assign INTSIG[x] = A[5]; etc.

This is why i have spare lines for. :)

Last missing to make whole of it to make sense to me are _IORD/_IOWR signals. How would I replicate this?

[terriblefire]

Last missing to make whole of it to make sense to me are _IORD/_IOWR signals. How would I replicate this?

IORD = Bus request + RW high
IORW = Bus Request + RW low

So you dont need to emulate these... this can be abstracted away.

[arkadiusz.makarenko]

Last missing to make whole of it to make sense to me are _IORD/_IOWR signals. How would I replicate this?

IORD = Bus request + RW high
IORW = Bus Request + RW low

So you dont need to emulate these... this can be abstracted away.

Can I just read only value of /RW then? I will be decoded address + RW + bits of Address line, so I would have all states required to emulate RTC?

[terriblefire]

IORD = Bus request + RW high
IORW = Bus Request + RW low

So you dont need to emulate these... this can be abstracted away.

Can I just read only value of /RW then? I will be decoded address + RW + bits of Address line, so I would have all states required to emulate RTC?

Yeah i think thats the case. I cant remember if there was also a BUSREQ pin?

[arkadiusz.makarenko]

Can I just read only value of /RW then? I will be decoded address + RW + bits of Address line, so I would have all states required to emulate RTC?

Yeah i think thats the case. I cant remember if there was also a BUSREQ pin?

Those are available on edge connection, but a lot of ?? on descriptions.

111 /CPU_BR CPU bus request??
112 /EXP_BG Expansion bus granted??
113 /CPU_BG CPU bus granted??
114 /EXP_BR Expansion bus request??

I will grab and test it on A1200 on clockport first if I manage to emulate MSM6242 then I will go back and test it on Riser (less moving parts)

[terriblefire]

No those are the arb signals...

The interrupt should be enough.

[terriblefire]

Im happy to test this out on my CD32 when you're ready. I still have this riser and a CD32 here.

[arkadiusz.makarenko]

Im happy to test this out on my CD32 when you're ready. I still have this riser and a CD32 here.

As soon as I will have something to show...

[arkadiusz.makarenko]

:D

My first verilog that actually passed syntax check and I managed to program cpld

Code: Select all

module address_decoder(
    input [23:16] A,
    input A3,
    input A5,
    output INTSIG2,
    output INTSIG3,
    output INTSIG5
    );

assign INTSIG3 = A3;
assign INTSIG5 = A5;
assign INTSIG2 = A[23:16]==8'b1101_1100; //RTC registers at $DC0000 - $DCFFFF 


endmodule

and mappings

Code: Select all

NET "A3"  LOC = "P32"  ;
NET "A5"  LOC = "P34"  ;
NET "A<16>"  LOC = "P47"  ;
NET "A<17>"  LOC = "P48"  ;
NET "A<18>"  LOC = "P57"  ;
NET "A<19>"  LOC = "P56"  ;
NET "A<20>"  LOC = "P51"  ;
NET "A<21>"  LOC = "P52"  ;
NET "A<22>"  LOC = "P50"  ;
NET "A<23>"  LOC = "P49"  ;
NET "INTSIG2"  LOC = "P23"  ;
NET "INTSIG3"  LOC = "P24"  ;
NET "INTSIG5"  LOC = "P12"  ;

[arkadiusz.makarenko]

I managed to detect RTC_SEL interrupt when looking for RTC clock in Amiga Tool Kit, so at least I know that this bit works.
I can read SOME addresses as well.
So it is time to try to put something on the bus.