PLD SDRAM controller ?

[exxos]

Edit: just thought, the controller would fit in the XC9572XL too -- that has only 72 IOs on the 100 pin version, but still more than enough. £4 chip instead!

Sounds like a plan. I was going with the SDRAM I found as JLC stock it (and can solder it) plus the buffers, not sure they sell the PLD, but at least it would just be 1 chip to solder.

More IO's may or may not be an advantage for PCB routing.. but I guess I could try with the smaller one first and see how it goes.

[Icky]

Looking at it seems like it can be made to fit. Definitely a 4 layer board though.

[Badwolf]

Edit: just thought, the controller would fit in the XC9572XL too -- that has only 72 IOs on the 100 pin version, but still more than enough. £4 chip instead!

Sounds like a plan. I was going with the SDRAM I found as JLC stock it (and can solder it) plus the buffers, not sure they sell the PLD, but at least it would just be 1 chip to solder.

More IO's may or may not be an advantage for PCB routing.. but I guess I could try with the smaller one first and see how it goes.

I'd be tempted to do the dev on the 100-pin XC95144XL then, when it's working, try to build it for the XC9572XL -- if it fits, use that for production.

They're the same footprint, same control and power pins, you just need to make sure you don't use an IO that doesn't exist on the 72. I'm basically doing that for my board. I'm using a 288, but it should fit in a 144 when I'm done.

BW.

[terriblefire]

I'd be tempted to do the dev on the 100-pin XC95144XL then, when it's working, try to build it for the XC9572XL -- if it fits, use that for production.

They're the same footprint, same control and power pins, you just need to make sure you don't use an IO that doesn't exist on the 72. I'm basically doing that for my board. I'm using a 288, but it should fit in a 144 when I'm done.

BW.

Careful with this. There are NC IO pins on the 72 vs 144! This bit me on the TF534. I thought all IO was available but when i used a 72 it gave me a cannot place an IO at pin X.Y.Z...

[exxos]

Careful with this. There are NC IO pins on the 72 vs 144! This bit me on the TF534. I thought all IO was available but when i used a 72 it have me a cannot place an IO at pin X.Y.Z...

I ran into that trap once as well.. Created the schematic with the more IO version then downgraded to a smaller one :roll:

[exxos]

I'd be tempted to do the dev on the 100-pin XC95144XL then, when it's working, try to build it for the XC9572XL -- if it fits, use that for production.

Yeah, might as well go with the more IO count version if its the same foot print anyway.

[Badwolf]

Careful with this. There are NC IO pins on the 72 vs 144! This bit me on the TF534. I thought all IO was available but when i used a 72 it have me a cannot place an IO at pin X.Y.Z...

Yep, 9 fewer, I believe. That's what I was getting at!

BW

[Badwolf]

I think my simplified SDRAM controller is pretty solid now. My remaining problems with higher speed seem to be hardware related (too any reflections causing oscillations on the data lines -- need to experiment with some termination on the data lines).

I've tried building it for the XC9572XL. It fits and requires 65 pins for 32 bit mode with two SDRAM chips, but can be reduced to 61 pins for single chip. It shouldn't be hard to adapt to 68k by subbing the SIZE lines for UDS/LDS either.

Code: Select all

cpldfit:  version P.20131013                        Xilinx Inc.
                                  Fitter Report
Design Name: DFB_SDRAM                           Date:  1-22-2021, 10:52AM
Device Used: XC9572XL-10-TQ100
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
48 /72  ( 67%) 174 /360  ( 48%) 143/216 ( 66%)   46 /72  ( 64%) 63 /72  ( 87%)

** Function Block Resources **

Function    Mcells      FB Inps     Pterms      IO          
Block       Used/Tot    Used/Tot    Used/Tot    Used/Tot    
FB1           9/18       37/54       52/90      14/18
FB2           8/18       29/54       30/90      16/18
FB3          18/18*      38/54       57/90      15/18
FB4          13/18       39/54       35/90      18/18*
             -----       -----       -----      -----    
             48/72      143/216     174/360     63/72 

* - Resource is exhausted

** Global Control Resources **

Code to date is attached, if it's any use to you @exxos.

BW.

[exxos]

Thanks @Bama very kind of you ! Hopefully I can make a start on a PCB for it. BTW would just DRAM work ?

[Badwolf]

Thanks @Bama very kind of you ! Hopefully I can make a start on a PCB for it. BTW would just DRAM work ?

Never done any work with straight-up DRAM, so couldn't really say but AFAIK the whole command concept is an SDRAM thing, so I doubt it.

Presumably the initialisation and the refresh sequences would be different at the very least. I'd have thought a CPLD would be overkill for DRAM, TBH.

Good luck. I'm guessing this is an Alt-RAM plug in for the STF? :)

BW.