What did you do & what's the current config?
FWIW I decided to take the CPLD out of the equation and basically DSACK[x] now go high-Z on FPU access allowing the two bodge wires I showed previously to drive the CPU pins directly.
So this is exactly the datasheet implementation.
It made no difference on my board. My FPU still tops out at 30MHz.
So next step was to experiment with a separate oscillator -- I disabled the FPUCLK entirely and fitted a second socket for the FPU osc. This at least feeds a proper 5V signal to the FPU. Again, no difference. Tops out at 30MHz.
I think I've a 30MHz chip.
So I've not learned much here other than going high-Z on FPU does work, so I can avoid the complications of routeing via the CPLD if I do another board revision.
BW

