REV 3 - REV 5 - The beginning (ST536)

[exxos]

Is the amount it detects always consistent?

Yep. I need to build up a new board :(

BTW, does this do what I think it does ? :lol:

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assign BUS_FREE = ({D[15:15]} != 16'b1);

[exxos]

Operation "solder socket" is now underway..

IMG_6371.JPG

IMG_6372.JPG

[Badwolf]

Is the amount it detects always consistent?

Yep. I need to build up a new board :(

BTW, does this do what I think it does ? :lol:

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assign BUS_FREE = ({D[15:15]} != 16'b1);

That sets wire BUS_FREE to be high when the single line D15 is anything other than binary "0000000000000001" and low when it is.

So I'd guess not! :lol:

What are you trying to do?

BW

[exxos]

That sets wire BUS_FREE to be high when the single line D15 is anything other than binary "0000000000000001" and low when it is.

So I'd guess not! :lol:

What are you trying to do?

dammit!! :lol:

I just want to try checking that all data lines are high before allowing RAM access... Currently it is two CPU clocks delays, one delay does not work, but I was thinking I could check the databus to see that did anything different..

[terriblefire]

BTW, does this do what I think it does ? :lol:

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assign BUS_FREE = ({D[15:15]} != 16'b1);

Surprised the compiler doesnt spit the dummy at that...

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assign BUS_FREE = ~D[15];

[exxos]

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assign BUS_FREE = ~D[15];

oh thanks, that makes much more sense!

[terriblefire]

Spend half an hour reading this

http://www.asic-world.com/verilog/verilog_one_day.html

[Badwolf]

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assign BUS_FREE = ~D[15];

oh thanks, that makes much more sense!

I still don't think that does what you want. D15 doesn't have a pull-up (does it?) and all this does is check if it's high.

I think you're meaning to check if the ST's bus has been pulled high?

How about:

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wire ST_BUS_ALL_HIGH;
assign ST_BUS_ALL_HIGH = ~&D[31:16]; // active low

I *think* this is a shortcut for "NOT ( D31 & D30 & D29 & ... & D16 )". So will only be low if they're all high (remember the ST's bus is D31:16 and AIUI the only half of the bus that's pulled high).

Obviously this will also be true whenever an FFFF is read from or written to any even ST RAM address or any multiple of 4 AltRAM address.

BW

[exxos]

Spend half an hour reading this

http://www.asic-world.com/verilog/verilog_one_day.html

I have looked at that site a lot but might as well be in Chinese. Pages of how stuff works doesn't really help when you have a specific problem and no example on how to do it. Even after spending hours looking around the Internet for solutions all I really come across is arguments on multiple ways of doing something which I think should be relatively simple. I'm sure that site explains things very well, but which of the hundred pages actually has an example of what I actually want to do on it, there is absolutely no way a novice like myself to know such things.

[exxos]

I think you're meaning to check if the ST's bus has been pulled high?

I just realised it is the upper bits which are actually on the ST bus D16-D31 on the CPU :roll:

I also just thought this has to be a latched condition as when the CPU accesses the bus it is obviously not all high any more.

Idea being that ram_delay3 will hold off ram_access until the bus is all high.. then it's allowed to run.. but it then has to remain in that state until the cycle is completed..

Obviously AS30 will set the FF to high when AS30 = 1.. When CPU accesses the bus the FF is allowed to run, and will latch BUS_FREE when its sees all datalines high..

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assign BUS_FREE = ~&D[31:16];
FDCP ff_dtack3r( .D(  BUS_FREE ), .C( CLK100M ), .PRE( AS30 ), .CLR( 1'b0 ), .Q( ram_delay3 ) );
wire ram_access = ram_decode | ram_delay3;