TOS RAM test routine ?

[exxos]

So I just removed the spaces before the include lines and now it has gone even more nuts :(

Capture.PNG

Think I am going to have to call it a day on this until @agranlund Returns and can just write a simpler routine for me.

[exxos]

@dml Not sure if this is your cup of tea or not but do you know anything about relocating ROM into TTram ? I mean all the code is basically done already here in MAPROM, but I cannot figure out at incorporate just the bits I want into TOS.

I mean allocating TTram and copying TOS into it should be relatively simple I think. A lot of checks were for various TOS versions etc which are just not needed anyway. TTram is already set up and FRB already done. Not bothered about relocating lower ram variables or anything at the moment which MAPROM does.

But it is setting up the MMU tables to do the redirect from TOS206 space to the new TTram based ROM. Which is the main problem. I cannot really imagine this would be too difficult for someone to do who actually knows what they are doing . Clearly this is not me,I obviously did try very hard though. :lol: :roll:

[Badwolf]

You're not going to be able to incorporate a RAM-based program into ROM trivially. For a start any relative variables won't work.

I never got much luck compiling the old Maprom with DEVPAC3.1, which is what it's intended to be build with, IIRC. I think I got it to work with vasm in a cross-compilation setting, though.

A small routine to copy ROM into FASTRAM is going to be pretty straightforward. Sorting out all the system variables and doing the MMU stuff would be where a program earns its corn (& the bit I can't help you with).

BW

[exxos]

You're not going to be able to incorporate a RAM-based program into ROM trivially. For a start any relative variables won't work.

A small routine to copy ROM into FASTRAM is going to be pretty straightforward. Sorting out all the system variables and doing the MMU stuff would be where a program earns its corn (& the bit I can't help you with).

As far as anything is concerned with the MMU in use, TOS still lives and runs from TOS206 space. I'm not really looking to incorporate the entire MAPROM code into TOS ( there just isn't room for starters).

But if you are saying this is simply not going to work no matter what then I have pretty much wasted the entirety of today trying to do just that :roll:

[Badwolf]

A small routine to copy ROM into FASTRAM is going to be pretty straightforward. Sorting out all the system variables and doing the MMU stuff would be where a program earns its corn (& the bit I can't help you with).

As far as anything is concerned with the MMU in use, TOS still lives and runs from TOS206 space.

I was talking about making sure your memory isn't stomped all over by adjusting the system variables. I'm not sure we're talking about the same thing here. Mind you if this code's executing far enough into OS boot, I suppose an Mxalloc would be sufficient.

But if you are saying this is simply not going to work no matter what then I have pretty much wasted the entirety of today trying to do just that :roll:

When I did my recent TOS hacking, I ported chunks of Anders' TT-RAM detection logic to ROM. It needed a fair bit of tinkering.

You can't do things like:-

Code: Select all

gTTRL_BushandlerOld	ds.l 1		; old bus error handler
...
	move.l	$8,gTTRL_BushandlerOld		; save old bus handler

Because that location you've just defined is read only. :)

BW

[exxos]

I was talking about making sure your memory isn't stomped all over by adjusting the system variables. I'm not sure we're talking about the same thing here. Mind you if this code's executing far enough into OS boot, I suppose an Mxalloc would be sufficient.

I was planning on running it after the memory test before it starts booting from Floppy / C:. This way ram and FRB are already set up and ready to go.At that point basically everything is initialised.

It would however cause a huge headache if I was to do this right at the start of the bootup sequence***. It of course will not help with the RAM speed test results. but I was merely trying to just get TOS relocated into TTram. as then nobody would really need MAPROM then. But at least for a "stock" system with a ST536.

*** I guess it could probably be possible to do it earlier on. Because it looks like TTram is zeroed to work out how much RAM there actually is before it starts testing it. It was a routine I had to fiddle with to fix the RAM amount being wrong in fact. Though maybe that could have been intentional to use the RAM area for something else in the first place.. As technically if the top of that RAM was never declared to the system, then "RAMTOP" could just be a little bit less and ROM reallocated to that space with the MMU. But one problem at a time...

Because that location you've just defined is read only. :)

Good point. Is why I need someone who knows what they are doing in cleaning up all the code and removing all the bits which are simply not needed. But could potentially be quicker just to rewrite the thing anyway.

[exxos]

So in actual fact this is the sort of stuff which is actually in MAPROM...

TOS

Code: Select all

mmurom_table:
/* tia: top level table (for 0x00000000-0xffffffff) */
        dc.l      TABLE(tib1)        /* for 0x00000000-0x0fffffff, use table tib1 */
        dc.l      PAGE($10000000)    /* map 0x10000000-0x7fffffff to the same */
        dc.l      PAGE($20000000)    /*   physical addresses, allow caching   */
        dc.l      PAGE($30000000)
        dc.l      PAGE($40000000)
        dc.l      PAGE($50000000)
        dc.l      PAGE($60000000)
        dc.l      PAGE($70000000)
        dc.l      PAGE_CI($80000000)   /* map 0x80000000-0xefffffff to the same */
        dc.l      PAGE_CI($90000000)   /*   physical addresses, DON'T allow caching */
        dc.l      PAGE_CI($a0000000)
        dc.l      PAGE_CI($b0000000)
        dc.l      PAGE_CI($c0000000)
        dc.l      PAGE_CI($d0000000)
        dc.l      PAGE_CI($e0000000)
        dc.l      TABLE(tib2)        /* for 0xf0000000-0xffffffff, use table tib2 */
/* tib1: second level table (for 0x00000000-0x0fffffff) */
        dc.l      TABLE(tic)         /* for 0x00000000-0x00ffffff, use table tic */
        dc.l      PAGE($01000000)    /* map 0x01000000-0x0fffffff to the same */
        dc.l      PAGE($02000000)    /*   physical addresses, allow caching   */
        dc.l      PAGE($03000000)
        dc.l      PAGE($04000000)
        dc.l      PAGE($05000000)
        dc.l      PAGE($06000000)
        dc.l      PAGE($07000000)
        dc.l      PAGE($08000000)
        dc.l      PAGE($09000000)
        dc.l      PAGE($0a000000)
        dc.l      PAGE($0b000000)
        dc.l      PAGE($0c000000)
        dc.l      PAGE($0d000000)
        dc.l      PAGE($0e000000)
        dc.l      PAGE($0f000000)
/* tib2: second-level table (for 0xf0000000-0xffffffff) */
        dc.l      PAGE_CI($00000000)  /* map 0xf0000000-0xfeffffff to the same */
        dc.l      PAGE_CI($01000000)  /*   physical addresses, DON'T allow caching */
        dc.l      PAGE_CI($02000000)
        dc.l      PAGE_CI($03000000)
        dc.l      PAGE_CI($04000000)
        dc.l      PAGE_CI($05000000)
        dc.l      PAGE_CI($06000000)
        dc.l      PAGE_CI($07000000)
        dc.l      PAGE_CI($08000000)
        dc.l      PAGE_CI($09000000)
        dc.l      PAGE_CI($0a000000)
        dc.l      PAGE_CI($0b000000)
        dc.l      PAGE_CI($0c000000)
        dc.l      PAGE_CI($0d000000)
        dc.l      PAGE_CI($0e000000)
        dc.l      TABLE(tic)           /* for 0xf0000000-0xffffffff, use table tic */
/* tic: third-level table for standard TT/Falcon addresses */
        dc.l      PAGE($00000000)      /* map 0xff000000-0xffefffff */
        dc.l      PAGE($00100000)      /*   0x00000000-0x00efffff, allow caching       */
        dc.l      PAGE($00200000)
        dc.l      PAGE($00300000)
        dc.l      PAGE($00400000)
        dc.l      PAGE($00500000)
        dc.l      PAGE($00600000)
        dc.l      PAGE($00700000)
        dc.l      PAGE($00800000)
        dc.l      PAGE($00900000)

MAPROM

Code: Select all

       PMMU030_TABLE	PMMU030_TABLE_TIB1	
        PMMU030_PAGE 	$10000000		
        PMMU030_PAGE	$20000000
        PMMU030_PAGE	$30000000
        PMMU030_PAGE	$40000000
        PMMU030_PAGE	$50000000
        PMMU030_PAGE	$60000000
        PMMU030_PAGE	$70000000
        PMMU030_PAGE_CI	$80000000		
        PMMU030_PAGE_CI	$90000000
        PMMU030_PAGE_CI	$a0000000
        PMMU030_PAGE_CI	$b0000000
        PMMU030_PAGE_CI	$c0000000
        PMMU030_PAGE_CI	$d0000000
        PMMU030_PAGE_CI	$e0000000
        PMMU030_TABLE	PMMU030_TABLE_TIB2	


        PMMU030_TABLE	PMMU030_TABLE_TIC	
        PMMU030_PAGE	$01000000		
        PMMU030_PAGE	$02000000
        PMMU030_PAGE	$03000000
        PMMU030_PAGE	$04000000
        PMMU030_PAGE	$05000000
        PMMU030_PAGE	$06000000
        PMMU030_PAGE	$07000000
        PMMU030_PAGE	$08000000
        PMMU030_PAGE	$09000000
        PMMU030_PAGE	$0a000000
        PMMU030_PAGE	$0b000000
        PMMU030_PAGE	$0c000000
        PMMU030_PAGE	$0d000000
        PMMU030_PAGE	$0e000000
        PMMU030_PAGE	$0f000000


        PMMU030_PAGE_CI	$f0000000		
        PMMU030_PAGE_CI	$f1000000
        PMMU030_PAGE_CI	$f2000000
        PMMU030_PAGE_CI	$f3000000
        PMMU030_PAGE_CI	$f4000000
        PMMU030_PAGE_CI	$f5000000
        PMMU030_PAGE_CI	$f6000000
        PMMU030_PAGE_CI	$f7000000
        PMMU030_PAGE_CI	$f8000000
        PMMU030_PAGE_CI	$f9000000
        PMMU030_PAGE_CI	$fa000000
        PMMU030_PAGE_CI	$fb000000
        PMMU030_PAGE_CI	$fc000000
        PMMU030_PAGE_CI	$fd000000
        PMMU030_PAGE_CI	$fe000000
        PMMU030_TABLE	PMMU030_TABLE_TIC	

	

		IFEQ OPT_STRAM_CI
	        PMMU030_PAGE	$00000000
	        PMMU030_PAGE	$00100000
	        PMMU030_PAGE	$00200000
	        PMMU030_PAGE	$00300000
		ENDC
		IFNE OPT_STRAM_CI
	        PMMU030_PAGE_CI	$00000000		
	        PMMU030_PAGE_CI	$00100000		
	        PMMU030_PAGE_CI	$00200000		
	        PMMU030_PAGE_CI	$00300000		
		ENDC
        PMMU030_PAGE	$00400000
        PMMU030_PAGE	$00500000
        PMMU030_PAGE	$00600000
        PMMU030_PAGE	$00700000
        PMMU030_PAGE	$00800000
        PMMU030_PAGE	$00900000
        PMMU030_PAGE	$00a00000
        PMMU030_PAGE	$00b00000
        PMMU030_PAGE_CI	$00c00000		
        PMMU030_PAGE_CI	$00d00000		
        PMMU030_PAGE	$00e00000
        PMMU030_PAGE_CI	$00f00000		

No idea how it gets to redirect TOS into TTram though :shrug:

[Badwolf]

I did try looking at the PMMU in the past, but it hurt my brain and I never got to the point of it making more than conceptual sense, I'm afraid. :lol:

I think by the stage you're talking about, MXAlloc will be available, but I think there's something subtle about reset you need to take into account. Also I don't know what happens if something else wants to use the PMMU. Presumably it'd just fall back to the hardware ROM, so that should be safe.

BW

[exxos]

I did try looking at the PMMU in the past, but it hurt my brain and I never got to the point of it making more than conceptual sense, I'm afraid. :lol:

I will go with what my old electronics tutor used to say, "it is just too simple to understand" :lol:

I think by the stage you're talking about, MXAlloc will be available, but I think there's something subtle about reset you need to take into account. Also I don't know what happens if something else wants to use the PMMU. Presumably it'd just fall back to the hardware ROM, so that should be safe.

MMU is initialised quite early on, before system variables and cookie jar. But I guess I could just move the initialisation further down somewhere anyway.

There is loads of fixes to do with reset and keeping the MMU "as it was" and not resetting it... But I don't think reset currently works with the current configuration of the ST536 stuff anyway. Not really got that far yet. :lol:

[exxos]

@Badwolf A bit of light reading https://mikro.naprvyraz.sk/docs/Coding/ ... ie/MMU.TXT :lol: