Top right from the top or bottom? Do you mean chip northeast?
Anyway, I made a mistake -- I forgot to reset OPTION2 so the better result was with CPU not slowing down. Fitted OPTION2 and it failed on the first ftrig function again :/
BW



Ah ok, I see. Thanks for that. Will have to have a think about how all that trades-off if capacitance does prove the key.exxos wrote: 11 Nov 2022 21:58 I managed to load your files in ki-cad @Badwolf ..
... snip ...
So basically the white circles are where you should put small vias.. And the two red tracks denoting lower inductance path. He should be as straight as possible. Of course the capacitor should be moved as physically close to the pin as possible... And every power pin should have its own capacitor.. I generally use 2.2uF these days instead of 100nf.


:lol:

These things can be a royal PITA. I guess technically the impedance from the pin directly connected to VCC is lower than the impedance to the capacitor. Basically would mean removing the capacitors would have little or no effect on that basis.Badwolf wrote: 11 Nov 2022 22:16 Ah ok, I see. Thanks for that. Will have to have a think about how all that trades-off if capacitance does prove the key.

I knew I should have used the SMD sockets!exxos wrote: 11 Nov 2022 22:27 Also technically, VCC plane should be connected to the capacitor directly, but then the FPU VCC pins connected to the capacitor directly and not actually stitched to the VCC plane directly. If that makes sense...

But they are harder to solder :lol:


:chairsmack:Badwolf wrote: 11 Nov 2022 22:42 There's still an alternative (I used it on r3): if you want an FPU you connect specially provided pad to pin 3 on U62. That will let you use the internal FPU at 16MHz and shut-yer-noise.
Then I don't have to put any capacitors on any FPU sockets! :lol:
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