Smonson's slow H4 build

[exxos]

Does this give sufficient delay though?

You don't need to delay it, not unless you're using a booster to speed up ROM ( but that can be fixed in the booster anyway) , as the CPU will not pick up the data for 100+ns anyway.

[Smonson]

You don't need to bother with LDS/UDS for ROM.

Indeed, UDS and LDS are for writes only.

What about /OE though? Just tie it to ground?

If you are just using U4 for DTACK.. I really would not bother, just use a diode and tie to ROM_OE...

Yes, I believe so. That part is from the schematic provided by the original author (Ted Rossin). By ROM_OE, do you mean LDS/UDS?

[exxos]

What about /OE though? Just tie it to ground?

You can tie CE to GND.. OE is used to enable the ROM.. then put a diode to The same signal with a diode then you can pull DTACK low as well.

[stephen_usher]

You don't need to bother with LDS/UDS for ROM.

Indeed, UDS and LDS are for writes only.

What about /OE though? Just tie it to ground?

I used the GAL to do the address decoding, which controls /OE and the /AS line to run /CE on the ROM. (This matches the timing diagram as /CE should be before /OE.) This meant that the ROM was primed to output whenever an address appeared on the bus. It was then up to the GAL to decode the address or /ROM2 along with /RW to determine if it's a read operation so as to enable the output from the ROM (/ROE in my schematic). This same signal was used to enable /DTACK via the 74LS244.

[Smonson]

You can tie CE to GND.. OE is used to enable the ROM.. then put a diode to The same signal with a diode then you can pull DTACK low as well.

Ah, got it. Like this, yeah? (ignoring the signal naming of "CE" which is now misleading)

256krom-2.png (67.41 KiB) Viewed 10542 times

[Smonson]

I used the GAL to do the address decoding, which controls /OE and the /AS line to run /CE on the ROM. (This matches the timing diagram as /CE should be before /OE.) This meant that the ROM was primed to output whenever an address appeared on the bus. It was then up to the GAL to decode the address or /ROM2 along with /RW to determine if it's a read operation so as to enable the output from the ROM (/ROE in my schematic). This same signal was used to enable /DTACK via the 74LS244.

I could go down the custom route using a cheap CPLD, but using "F" high-speed logic seemed a lot more bullet-proof. I also can't stand soldering the EQFP packages on MAX Vs

[exxos]

Ah, got it. Like this, yeah? (ignoring the signal naming of "CE" which is now misleading)

Yep!

But CE should be OE on the diode signal

[Smonson]

Yep!

But CE should be OE on the diode signal

Sweet, thanks! Let's just pretend that says OE there. It's just a net name!

[exxos]

but using "F" high-speed logic seemed a lot more bullet-proof.

For this particular application, I really would suggest using slower LS types... With them being lower power and slower they are a lot less "noisy".

[Smonson]

For this particular application, I really would suggest using slower LS types... With them being lower power and slower they are a lot less "noisy".

Alright, I'll take your advice on that too. Thanks again!