Wanted: an old SILOS primitive library (pri150ww.lib)

[exxos]

Curious what you meant by it being a problem back then though, what did you run into?

[alexh]

I think ijor's talking about how designs like this could be susceptible to things such as process, voltage and temperature variations where one chip would work and another wouldn't?

The tools they had back then for timing digital circuits probably didn't yield meaningful results when you did things like this and rules had to be disabled hiding potential mistakes?

Netlists don't always contain the information about layout. Often timing fixes needed to be applied to digital designs during layout. They would change cell drive strength, modify track lengths, add buffers etc. to fix issues in the original design