Atari ST OPL3 cart schematics

[Badwolf]

Sorry -- daughter's not been well today. Not really had time to read all this properly. Responding a bit ad-hoc.

Need for this latch was purely to save state of adress lines to have certain pattern set on OPL3 data / address lines, after setting this I need to (assert /WR low or high OPL3 for certain time to set either address to which I'm writing data and next the value).

Ah, so you have to hold the address and data lines and toggle a pin?

I'd have to have a look at the data sheet, but yes, that might need a latch depending on the timing diagram.

Here is sample, which TOri has sent me (with A0 taken from LDS (,which is active low) and is our /WR strobe):
We want to set $01 adress register YM262 (A0=0, A1=0) - LSI TEST (Array 0)
1. We read back from #$FA0101 to d0, this will set 01 - data, 01 - adress (H - /WR) on latches
2. We turn off /WR by clearing /WR to 0 - low state
3. (we idling if needed)
4. We turn on /WR by setting /WR to 1 - high state
We need to repeat similar procedure to write to previously selected OPL3 address some data..

OK, without reading the YM262 data sheet, I'd just suggest using A1 for OPL_WR as then you don't need to synthesise A0. Nothing changes other than the addresses you use.

Instead of 0xFA0101 and 0xFA0100, you'd just use 0xFA0102 and 0xFA0100 and a word or byte read would both work, although I'd use UDS for simplicity.

If you want to expand to having two chips why not just use ROM4 for the second chip's CS line? Your address ranges change to 0xFBxxxx and everything doubles up. :)

They have used filmic capacitors to reduce noise on the board, there's no electrolitic caps (I probably will add them, but couldn't find proper footprint in KiCad).

Aha yeah film caps would also work, but I doubt they fit into that tiny SMD footprint. Have a look at the CP_Elec* series in CAPACITOR_SMD library or C_Radial* series in CAPACITOR_THT.


BW

[tOriman]

Hi,

In my last PM to nokturnal I suggest use of \ROM3 as \WR so any read from #$FBxxxx should write data stored in registers. Of course - system M68k doesn' have A0 address line, hahaha (I made stoopid mistake there)

So it might look like this:

[OPL_A0 - Atari A2, OPL A1 - Atari A3]

We need to write $05 to LSI_TEST register so,

1. readback from #$FA0100 - SET ADDRESS of LSI_TEST [$01] - OPL_A0=0, OPL_A1=0 (array 0)
2. pause if needed
3. readback from #$FB0000 - creation of \WR signal for YM262
4. readback from #$FA0504 - SET DATA - OPL_A0=1, OPL_A1=0 (write $5 to previously selected address [#$01] in array 0)
5. pause if needed
6. readback from #$FB0000 - creation of \WR signal for YM262

That's all. It looks good, but this is a proposal only and should be tested in a prototype.

tOri

P.S. btw. here is no need to use byte addressing. It should be always word addressing mode.

[nokturnal]

This is R/W timing:
Tww - 100ns,
Twds - 10ns
Twdh - 20ns

opl3Timing.png

We don't care about /CS, we just hold it low all the time (like on OPL3LPT). So, we set A0-1 (A1 is missing on chart, but we need to set it), \WR has to be held down (10ns at least), d0-7 data set, /WR released and data lines need to be held for some time(but we don't worry about it i guess).

@BadWolf: Yes, second 0xFBxxxx unit is also an option, but I would like to do it little differently by adding extra data line (A3, after A2), which will decide if we want to write to first or second opl chip/unit. There could be another line which could decide about operation mode. We could write same data to two opl chips at once(or with programmable delay(?)), so they would play in unison without extra cpu effort (we write as to single chip) or treat second chip independently with explicit cpu writes for unit 0/1 like it was done in OPL3 Duo!
And omitting A0 synthesis is nice, I have few free lines left. I don't understand, why I was so attached to this A0 generation idea. Maybe to have clear mapping m68k A0 bus to A0 register line on paper :)...

@tOriman After a little deliberation I don't like making /WR on 0xFBxxxx write, because I'm losing control over /WR state and how long I'm holding it. Same interface could be used with OPL2 (which is inferior, I know), but similar driver could be used as on OPL3 (omitting only A1(or not) and using different delays, I have done similar thing with OPL2LPT and OPL3LPT).

[Badwolf]

This is R/W timing:
Tww - 100ns,
Twds - 10ns
Twdh - 20ns
opl3Timing.png

The only one there I think that matters is Tww of 100ns.

If you drive it from a combination of ROM3 and A1 (if you want to identify chips with on A1, A2 etc.) then the minimum assertion time for an ST would be two clock cycles. At 8MHz that's 250ns. Plenty enough. I think, therefore you can drop the latches and it'll work on machines up to 20MHz. Might need latches for TT compatibility. But for a prototype? I'd drop 'em. More complicated.

In my last PM to nokturnal I suggest use of \ROM3 as \WR so any read from #$FBxxxx should write data stored in registers. Of course - system M68k doesn' have A0 address line, hahaha (I made stoopid mistake there)

I think that's what I'd do for a first version too.

:thumbup:

BW

[nokturnal]

@Badwolf I could prepare two versions with and without latches to see how everything behaves. But in the end I would like to have compatibility with faster machines too. Simpler version could be an option for people with standard machines (who know they will never, ever buy any accelerator ;-)).

I'm currently focusing on one chip version, but I've just want to have a place in design for hooking up second unit and try to not break existing programming interface (and avoid extra work, I expect that everything will behave the same as on OPL3 Duo board..).

Ok, so there's summary of improvements:
1) Add footprints for film capacitors in audio section. Try to use CP_Elec* series in CAPACITOR_SMD library or C_Radial* series in CAPACITOR_THT.
2) Cartridge port edge fix, to avoid issues.
3) Remove throughole vias on smt pads.
4) Decoupling capacitors: Remove uneccessary capacitors from digital signal chips. 100nF, one per power pin on each chip.
5) Cpu bus agnostic version: replace 74LS343 with 344. (maybe..)
6) 2nd board version (for unaccelerated machines): wire /ROM3 (or /ROM4) to OPL3 /WR and remove latches.
7) All small elements preferably on one board side (to reduce costs in case manufacturer solders all small parts).
8) Switch schematics to A3 to get more space.
9) Cpu bus agnostic version: Remove A0 synthesis from UDS/LDS and start adress bus assignment from A1.
10) As big and unbroken ground plane as possible - try to get all data tracks on the top side or have a four layer board. Separate audio planes (extra research needed how to do it properly).
11) Mounting holes for a case. (final version)

Shouldn't +5V track via be wider maybe (like cartridge pin width)?

Anyway @Badwolf @tOriman thank you for your suggestions, ideas and discussion. :thumbup:

[Badwolf]

@Badwolf I could prepare two versions with and without latches to see how everything behaves. But in the end I would like to have compatibility with faster machines too. Simpler version could be an option for people with standard machines (who know they will never, ever buy any accelerator ;-)).
...
Shouldn't +5V track via be wider maybe (like cartridge pin width)?

Anyway @Badwolf @tOriman thank you for your suggestions, ideas and discussion. :thumbup:

No worries.

If you're dead set on having a version with the latches for the TT (those figures are speculative BTW, I don't know the cartridge access time for the TT. Accelerators will slow down to use the cartridge port for the most part so shouldn't be affected), don't bother doing two boards. More hassle. Just do the one you want and iterate on it until it works. :)

Two boards would have different application interfaces, which is what you're trying to avoid elsewhere. One would need active on-off commands, one would just be single reads.

If space isn't at a premium my normal track widths will be 0.24mm for signals (allows you to fit a single trace between two 2.54mm pin headers) and 0.5mm for power.

If things are really tight then I'll go down to 0.16mm for signals and 0.32 for power -- but I'd normally be a four layers by then with a dedicated power and ground plane in the middle.

Oh! One thing I forgot to mention. You look like you've added some debugging headers to your board -- J3 and J4. Those look like 1.27mm pitch headers. Those will be *tiny* and probably nigh on impossible to probe, if that's your plan. 2.54mm headers are the 'normal' ones you'll see. Twice the size.

BW

[nokturnal]

@Badwolf Maybe you're right. Yes, I'm aware that those connectors are too small, but thanks for noticing it. I will have more space for them now ;).. Having separate planes for power/gnd isn't that bad idea, but I've newer designed anything with 2>layers. That might be fun :)...

[nokturnal]

@Badwolf @tOriman
I've made fixes to both schematics and pcb board:
- Reworked it to 4 layer version in the end after quick crash course(TOP,GND,+5V,BOTTOM), still I haven't separate audio / digital planes.
- Four capacitor footprints were replaced with WIMA ones (big red, final ones will be probably not that high, not very symetrically placed but ¯\_(ツ)_/¯), rest is sort of unchanged (smd, 603 parts).
- Removed latches completely. More space, pcb isn't long as train now. :) It could be smaller, but I could't find proper footprints for logic gates (I spare it for the final version). I have DIP versions and I don't want to spend money on extra parts.
- No mounting holes for case, prototype.
- Reworked cart edge. Should be better now. Tested against F030 port.
- All SMD parts are on the bottom.
- Unfortunately I didn't manage to keep all the signals on one side :(. Routing all the signals was hard enough and I suck at it..

I've had to add one missing thing, about which I've forgot - posibility to reset OPL3 via software, had to add not gate and dedicated one adress line for this. I could do it without gate and with 0xFBxxxx read(which is active low), but I've decided to go with adress line anyway (RESET /IC is active low).

fmST_v.8_front.png

fmST_v.8_back.png

The schematics and pcb design are in repo, so if you could take a look it would be great. Just sync to latest revision. Still have problem with finding source for clock generator in this kind of case, I hope that I will not have to improvise it with quartz resonator..

I wonder also if there will be a problem with those extra planes. Probably I need to specify max board thickness, because there will be issues with plugging cart in. I hope that 4 layer boar thickness will not exceed cartridge port plug size.

[DoG]

PCB for cartridge port should be 1,6mm. But that is standard PCB thickness so shouldn't be a problem. You could also file the edge on both sides at 45 degrees to make the cartridge slide in a bit easier in the port.

[nokturnal]

@DoG Even with more layers than 2? I have to see how they are doing whole manufacturing, I didn't invest much time into investigating it, maybe I should. And yes, I know filing 45 angle can improve port lifetime. It's rather mandatory, especially when it's not possible to get new cart ports these days.