TOS patch for 1.44MB floppy support ?

[exxos]

Does anyone know what register the dip switches are at ?

Seems I've looked at this before https://www.exxosforum.co.uk/forum/viewt ... 200#p31163

Seems just emulating the switches isn't enough. Looks like I was considering the register isn't even checked unless its found to be a STE based machine :roll:

[sporniket]

if there is no error, info-coach hints at $FF9200 (see https://info-coach.fr/atari/hardware/ST ... #joysticks )

edit : ha, you posted while I was re-reading info-coach :D

[exxos]

if there is no error, info-coach hints at $FF9200 (see https://info-coach.fr/atari/hardware/ST ... #joysticks )

edit : ha, you posted while I was re-reading info-coach :D

:lol: yep it's confused things as most docs just state the joystick stuff :roll:

I guess the idea currently is that because its not a STE, TOS never looks at those addresses, and never checks the dip switches. So I need to look at where in TOS the joystick stuff gets enabled.

It's looking more like it's going to have to have a TOS hack to get it to work, which is annoying when it gets to multiple builds of TOS206 :roll:

[troed]

Well we have the source to TOS 2.06 so it's easy to make a clean change. But it sounds a bit surprising that the HD floppy stuff wouldn't work on non-STE machines since Atari intended that TOS for the ST range too.

[troed]

I didn't have the equations for the MSTE PAL, but maybe someone else has. In any case, I decompiled the .JED and manually analyzed it a bit:

Code: Select all

; JED2EQN -- JEDEC file to Boolean Equations disassembler (Version V063)
; Copyright (c) National Semiconductor Corporation 1990-1993
; Disassembled from MSTE_UA2.JED. Date: 5-25-122
;$GALMODE MEDIUM

chip MSTE_UA2 GAL20V8

; note the inversion on A15 in the declaration
A4=1 A5=2 A6=3 A7=4 A8=5 A9=6 A10=7 A11=8 A12=9 A13=10 A14=11 GND=12 
/A15=13 i14=14 o15=15 f16=16 o17=17 o18=18 f19=19 A2=20 A3=21 
o22=22 i23=23 VCC=24 

@ues 4d53544520554132
@ptd unused

equations

; "DD/HD mode on MegaSTE at $FF860E (bits 0/1)" (Hatari)
; The 22V10 is what decodes bit 0/1, but this PAL should decode that address I thought.

; an AND gate ands A16-A23 together as XIO which also goes to the PAL22V10
; we assume all those need to be 1's
; it also uses FC0, FC1 and FC2 where FC2 always need to be 1 but the others can be 1/0 or 0/1
; the "unconnected" pin 19 need to be grounded for some reason

; this is the output that should decode ff860e
; 1111111110000110000011xx = 0xff860c/0xff860e <-- what we have
; 11111111100001100000111x = 0xff860e <-- what we should have
/o22 = /A5 * /A4 * /A6 * i23 * /A7 * A3 * /A8 * A2 * A9 * f19 * A10
      * /A11 * /A12 * f16 * /A13 * /i14 * /A14 * /A15
    + /A5 * /A4 * /A6 * /i23 * /A7 * A3 * /A8 * A2 * A9 * f19 * A10
      * /A11 * /A12 * f16 * /A13 * i14 * /A14 * /A15

o22.oe = vcc
/A3 = gnd
A3.oe = gnd
/A2 = gnd
A2.oe = gnd
/f19 = gnd
f19.oe = gnd

; this should be fc0dxx?
; 111111111100001xxxxxxxxx = 0xffc2xx-0xffc3xx
/o18 = /i23 * /A9 * A10 * A11 * A12 * f16 * A13 * i14 * A14 * /A15
    + i23 * /A9 * A10 * A11 * A12 * f16 * A13 * /i14 * A14 * /A15
o18.oe = vcc

; this should be ff8e20?
; 111111111000110000x000xx (A5 not used) = ff8c00-03 & ff8c20-23
/o17 = i2 * /A4 * /A6 * i23 * /A7 * /A3 * /A8 * /A2 * /A9 * A10 * A11
      * /A12 * f16 * /A13 * /i14 * /A14 * /A15
    + i2 * /A4 * /A6 * /i23 * /A7 * /A3 * /A8 * /A2 * /A9 * A10 * A11
      * /A12 * f16 * /A13 * i14 * /A14 * /A15
o17.oe = vcc
/f16 = gnd
f16.oe = gnd

; "XSCC"
; 111111111000110010000xxx = ff8c80-87
/o15 = /A5 * /A4 * /A6 * i23 * A7 * /A3 * /A8 * /A9 * A10 * A11 * /A12
      * f16 * /A13 * /i14 * /A14 * /A15
    + /A5 * /A4 * /A6 * /i23 * A7 * /A3 * /A8 * /A9 * A10 * A11 * /A12
      * f16 * /A13 * i14 * /A14 * /A15
o15.oe = vcc

[exxos]

No idea whats going on. In the sources it does look like its accessing the register , but on the MSTE schematic, bit 7 is "XLAN" so doesn't seem to have anything to do with the floppy.

I'm building a new TOS to just skip the register test without the other stuff i've enabled to see if raw register access works..

EDIT:

OK I don't believe it, but that worked. I need to revisit what I did with flashy-clock to see why that didn't work before.

[agranlund]

I guess the idea currently is that because its not a STE, TOS never looks at those addresses, and never checks the dip switches. So I need to look at where in TOS the joystick stuff gets enabled.

Just a few lines above the code you posted earlier it checks an internal "STEFlag" variable to determine if it should read those dip switches or not :)

STEFlag is set earlier in the startup code but I doubt you want to change that particular variable since it probably effects other things too.

Anyway, if it's not STE then it will not read the dip switch register but rather treat them as 1.
(There are some checks for STEFlag in floppy.inc too)

Code: Select all

  move.b    #$7f,d0		**** put default dip settings in D0 (0x7f == DIP switch 6 is 1 == no HD Floppy)
  tst.b     STEFlag		**** Is it an STE?
  bne.s     cooSTE		**** no it's not, skip to cooSTE without reading dip switches
  ......
  move.w    (STConfig).w,d0	**** We are an STE. Read the actual dip switches from STConfig (0xFF9200) into D0
  lsr.w     #8,d0
  ......
cooSTE:
  ......     
  btst      #6,d0		**** test bit 6 of D0 which is dip switch 6 (or always 1 in the case of non-STE)
  bne.s     cooFDC		/* (punt - no HD floppy) */
  move.b    #8,dsb		/* select HD density for drive A */
  move.l    #'_FDC',(a0)+	/* setup FDC cookie: Floppy disk controller */
  move.l    #$01415443,(a0)+	/* 'ATC' | (1 << 24) */
cooFDC:

[exxos]

Just a few lines above the code you posted earlier it checks an internal "STEFlag" variable to determine if it should read those dip switches or not :)]

That's what I thought originally but just ignoring this check made it work..https://www.exxosforum.co.uk/forum/viewt ... 575#p85575

[agranlund]

That's what I thought originally but just ignoring this check made it work..https://www.exxosforum.co.uk/forum/viewt ... 575#p85575

Nice one!

[troed]

Nice! Although it does seem as you mix up the DIP switch (HD floppy option in GEM) with the register decoded by the PAL that allows TOS to switch frequency?

I don't remember where I've read about which address the PAL listens to before, but the equations I posted plus schematics should be able to give us that.