TF536 and H4 Benchmark

[exxos]

TF536 ST edition - MAPROM1.8E - TOS206

IMG_0358.JPG

[Cyprian]

Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF

[exxos]

Interesting figures.

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF

No idea. But IIRC on the falcon the data cache on made the tests about 3% slower. So caches don't always help.

[alexh]

I wonder why the best results are with Instruction Cache Off. - D ON, I OFF

Cache line fills from DRAM take more time than a single instruction fetch. Even with 030 burst mode. That time is usually made up when the CPU executes the full line from CACHE and doesn't read from DRAM. If the CPU doesn't execute a full cache line, perhaps due to branching, then the benefit of the cache is reduced. Even more so if that cache line becomes invalidated and re-filled due to code alignment. (Sometimes called cache thrashing) So depending on the code, iCache performance can be worse than no iCache.

[exxos]

The falcon does odd stuff as well https://www.exxosforum.co.uk/forum/viewt ... 1038#p7924