Let's build a CTPCI!

[foft]

btw. some times ago I heard about some problems with CTPCI. What kind they were and were they resolved in that version?

Do you mean the dma problems?

[Cyprian]

btw. some times ago I heard about some problems with CTPCI. What kind they were and were they resolved in that version?

Do you mean the dma problems?

I just read some opinion over Atari-Forum but without the context. I don't know the details, hence my previous question.

[Steve]

Yeah it is confusing, apparently the designer was looking for some strange bug for a long time and eventually gave up... But whatever this bug was, or the problems it caused, nobody speaks about.

[mikro]

It's mentioned in readme.txt:

Code: Select all

Hardware CTPCI bugs list:
-------------------------
- PCI 33MHz boards not works, for example USB generic NEC board
  go to "unrecoverable PCI error" and set "Parity error".
  => use only graphics boards who are 33/66 MHz compatible (more 
  signal tolerance).
- Interrupts not works, to confirm (maybe the real cause is the first 
  problem). Local interrupts can't work.
- DMA writing sometimes freeze the system (easy to create with 
  MagiC/NVDI real time moving window.
  => disable DMA with CT650CONF.CPX.
- DMA reading crashes the system (not used actually).
- Bus mastering for works for same reason.
- PCI arbitration not works, for example if you want use Video RAM 
  with USB board (maybe the real cause is the first problem).

So actually the best is to install ONLY the Radeon board.

Also, there is a good log at http://didier.mequignon.free.fr/ct60/ctpci-e.htm, giving some hope in February 2012:

On CTPCI fixed PEND register bits test inverted, and finally revoved this test who can caused loop inside a PCI interrupt
Tried again, with the latest jedec file for the CTPCI (CTPCI_1L), the PCI/PCIe adapter and the USB2 PCIe board. It's better, interrupts works fine and the ethernet OZK RTL8139 driver runs, but I have freezes with ethernet and the USB Mass Storage (most of time when the DMA writes to the local RAM). Add delays loops seems reduce problems but slow down transfers, for example on USB you must replace the 1uS delay between two status register reading by a 10 mS delay, and for ethernet I used (just for test) an interrupt task with the OZK RTL8139 driver who add a delay after the interrupt. It's not a reliable solution for a final release (too hardware dependent).

but ending with the pessimistic note from November 2012:

Hardware update with the latest jedec file CTPCI_1N.JED, but the hardware dma lock workaround not fix the problems with USB Mass Storage transfers or an Ethernet PCI board.

Hopefully, the 1N he is talking about is the same I found in Rodolphe's archive: https://mikrosk.github.io/ct60tos/ctpci/english/dev.htm

[foft]

Thanks for the detailed info mikro.

It's interesting there are so many errors, since its a custom chip that actually does the PCI communication. So I'd expect issues to be on the CT60->PCI9054 side. Anyway the core Radeon video works well as I understand it. I'm just going for that - to start with at least. I think I'd find the whole thing easier to debug with a decent FPGA instead of 3 xilinx CPLD chips! Perhaps we should make that and use PCI express too instead (https://hackaday.com/2023/03/14/pcie-fo ... ore-578784).

Any the parts arrived today, so decided to start with the easy part -> yes, just one slot for now and I still need to populate the resistors (errrr, what should R6 and R7 be, they are not on the list of parts so perhaps not populated?!) + buy the missing J8!:

CTPCI_slotspic1.jpg (253.08 KiB) Viewed 2647 times

[foft]

I couldn't resist starting the main board, I decided to start with the resistor arrays.

This is how not to do it, put TOO much paste on . I'm not very good at applying thin paste without a stencil, need to improve here:

ctpci_too_much_paste.JPG (222.17 KiB) Viewed 2627 times

Which led to a bridge on ... like every array. So I used some braid and ended up with this. Not too bad though needs a little tidy and a fair bit of cleaning:

CTPCI_resistor_arrays.JPG (221.87 KiB) Viewed 2627 times

[foft]

Here are the aligned gerbers that I sent to pcbway (the original ones had offset drills and other strange offsets in some layers...). I don't yet know if the boards are correct, but visibly they look to be. As for the power planes, I can detect connections where I'd expect it to go via the two inner layers.

I bought ViewMate Deluxe to edit them, which seems pretty good for basic editing, it did a lot more than I needed.

[Cyprian]

It's mentioned in readme.txt:

thanks mikro

[alexh]

Exciting

[HigashiJun]

Good !

Keep us informed of your progress.