Raven. A homemade Atari-like computer

[agranlund]

Got struck with an idea while driving home from work and had to try it..

It's not a crazy performance bump, but for only a few lines of code it's not a bad free performance boost.
For now only applied on the SVGA driver but I should be able to make this global so it effects ET4000 and Mach as well.
There are further optimisations which could be made in the same spirit but requires more work.

Cirrus GD5434 now vs previous driver:

gd5434_ci_vs_cp.png (898.67 KiB) Viewed 128 times

gd5434_ci.png (901.7 KiB) Viewed 128 times

gd5434_ci_vs_cp_kronos.png (562.14 KiB) Viewed 128 times

[PhilC]

@agranlund that's a pretty good increase for just a few lines of code.

[agranlund]

@agranlund that's a pretty good increase for just a few lines of code.

Yep, I realised if I tag the vram pages as cache-inhibited-imprecise to take advantage of the storebuffer fifo then the cpu can keep doing a little bit of meaningful work while an ISA transfer is happening.

[PhilC]

@agranlund that's a pretty good increase for just a few lines of code.

Yep, I realised if I tag the vram pages as cache-inhibited-imprecise to take advantage of the storebuffer fifo then the cpu can keep doing a little bit of meaningful work while an ISA transfer is happening.

I wish I had room in my brain for stuff like that, let alone coming up with the idea whilst driving home

[mikro]

Yep, I realised if I tag the vram pages as cache-inhibited-imprecise to take advantage of the storebuffer fifo then the cpu can keep doing a little bit of meaningful work while an ISA transfer is happening.

You could have asked me, I did the same for CTPCI and SuperVidel years ago.

[agranlund]

Yep, I realised if I tag the vram pages as cache-inhibited-imprecise to take advantage of the storebuffer fifo then the cpu can keep doing a little bit of meaningful work while an ISA transfer is happening.

You could have asked me, I did the same for CTPCI and SuperVidel years ago.

Actually, yes! It's hard to ask about what you don't know but yes, it makes sense you did the same for those way back then
Probably worth me having a look at more of those sources in case there are other nice tidbits to learn from.
Or if you still have some ancient knowledge of other clever things that was done for CT60/PCI/SV that I could benefit from.

[mikro]

It's hard to ask about what you don't know but yes, it makes sense you did the same for those way back then

Fair point.

Probably worth me having a look at more of those sources in case there are other nice tidbits to learn from.

Actually, there is nothing to look at. I had a conversation with the Nature brothers back in 2014 where they mentioned that they are disabling cache for the whole SV memory area. I looked into 68060 UM how it's done and discovered that there are two models, precise and imprecise. So I just tried to change the PMMU to mark them as imprecise and voila. However the precise model has its use (naturally), for instance for areas which work with DMA you can't have it as imprecise.

Or if you still have some ancient knowledge of other clever things that was done for CT60/PCI/SV that I could benefit from.

Haha. The only thing I can think of is my measurements, as published on AF: https://www.atari-forum.com/viewtopic.p ... 85#p478885 & https://www.atari-forum.com/viewtopic.p ... 89#p478889.

TL; DR version is that: always use move16 when copying between TT and VRAM (any combination) and always use move.l when copying to ST RAM.