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officer960's H5 C1 build

Share your building progress here!
officer960
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Re: officer960's H5 C1 build

Post by officer960 »

Looked in the store, but not sure which item you're referring to, what's the item # on it?
H5C1, H5C5B, 1040 ST, Mega ST, STe, Mega STe, Falcon, TT030, Amiga 2k V2+, Amiga 2k Video Toaster GVP030, Amiga 500, Amiga 500+ V2, Amiga 500+ Firebird V4, Amiga 1200 PiStorm, FPGA: V4SA, MiST, MiSTer, UnAmiga, U64 Elite
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Re: officer960's H5 C1 build

Post by exxos »

officer960 wrote: 12 Aug 2025 21:16 Looked in the store, but not sure which item you're referring to, what's the item # on it?
https://www.exxosforum.co.uk/atari/store2/#0290
officer960
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Re: officer960's H5 C1 build

Post by officer960 »

At the risk of making this thread confusing, I'm going to post everything related to WS (wake state) testing here instead of splitting it between my H5C1 and H5C5B Build posts. My guess is either C1 or C5B would have the same results with the same chip/CPU/accelerator combo.

C1-Config 1
IMP Shifter C070713-002, IMP DMA C100110-001, IMP MMU C100109-001, IMP GLUE C070714-001 (all 1987 Date Codes): WS3 PLCC 68000 Enchanted Land, DHS Demo's #1 & #2 graphics seem perfectly stable.
C1-Config 2
IMP Shifter C070713-002, IMP DMA C100110-001, IMP MMU C100109-001, IMP GLUE C070714-001 (all 1987 Date Codes): WS3 PLCC 68000, Exxos Booster configured as ROM Decoder/Booster Disabled. Enchanted Land, DHS Demo's #1 & #2 graphics seem perfectly stable.
C1-Config 3
IMP Shifter C070713-002, IMP DMA C100110-001, IMP MMU C100109-001, IMP GLUE C070714-001 (all 1987 Date Codes): WS3 DIP 68000 on Exxos Booster configured as ROM Decoder, Booster set at 8MHz. Enchanted Land, DHS Demo's #1 & #2 graphics are unstable and glitched.

C5B-Config 1
Shifter C025914-38A, DMA C025913-38, MMU C025912-38, GLUE C025915: WS?[could not be tested] DMA confirmed bad - no floppy or ACSI drives detected
C5B-Config 2
Shifter C025914-38A, IMP DMA 100110-001 (1987), IMP MMU C100109-001 (1987), IMP GLUE C070714-001 (1987): WS?[didn't test due to unstable video] AdSpeed 16MHz accelerator. Game/Demo graphics were much more stable but did exhibit some graphical glitches and was having issues with RGBtoHDMI getting a video sync at low, medium, high resolution. Video sync "ok" with standard ST video cable on 15khz monitor.
C5B-Config 3
Shifter C025914-38A, DMA C025913-38, MMU C025912-38, GLUE C025915-38A: WS3 with PLCC 68000FN8 or PLCC 68HC000EI20. Enchanted Land, DHS Demo's #1 & #2 graphics run perfectly stable. RGBtoHDMI perfectly stable.
C5B-Config 4
Shifter C025914-38A, DMA C025913-38, MMU C025912-38, GLUE C025915-38A: WS2 with AdSpeed 16MHz accelerator set at 16 or 8MHz. 8MHz Enchanted Land, DHS Demo's #1 & #2 graphics run perfectly stable. RGBtoHDMI perfectly stable.

Notes: Initial testing on C5B had issues due to bad DMA and flaky MMU. I straightened the legs on the MMU and it seemed to work but I was still getting sync issues with RGBtoHDMI and dug out different MMU/GLUE to be sure. I think that there are issues of mixing IMP chips with non-IMP chips.

I did not test the Exxos accelerator in the C5B due to it reporting WS3 regardless of the chipset or CPU used.

Something in the AdSpeed changed Wake State in the C5B from WS3 to WS2 with the same chipset (config #3 & #4).
H5C1, H5C5B, 1040 ST, Mega ST, STe, Mega STe, Falcon, TT030, Amiga 2k V2+, Amiga 2k Video Toaster GVP030, Amiga 500, Amiga 500+ V2, Amiga 500+ Firebird V4, Amiga 1200 PiStorm, FPGA: V4SA, MiST, MiSTer, UnAmiga, U64 Elite
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Re: officer960's H5 C1 build

Post by exxos »

Thanks for doing the tests. @ijor May be interested in the results.

If you could use one of the 68K sockets to pickup the system clock (8mhz) then compare adspeed vs my booster on the CPU clock itself. Mine will be something like 10ns lagging (never measured it) but maybe adspeed has advanced the clock to end up with different WS..

The only slight problem is that sometimes the wait states can change between power-ups. Though I presume it is something to do with the clock sync where the issue is stemming from.
officer960
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Re: officer960's H5 C1 build

Post by officer960 »

exxos wrote: 13 Aug 2025 21:37 Thanks for doing the tests. @ijor May be interested in the results.

If you could use one of the 68K sockets to pickup the system clock (8mhz) then compare adspeed vs my booster on the CPU clock itself. Mine will be something like 10ns lagging (never measured it) but maybe adspeed has advanced the clock to end up with different WS..

The only slight problem is that sometimes the wait states can change between power-ups. Though I presume it is something to do with the clock sync where the issue is stemming from.
I will need to purchase (and learn to use) a scope. I know there are "cheap" digital ones now but I wouldn't even know which one to get. If you have any suggestions for a good enough one that won't force me to refinance my house I'd take the plunge.

During initial testing a couple weeks ago on the C5B, I damaged one of my AdSpeed accelerators prying it out of my Mega ST :oops: . I cracked a tiny SMD resistor and SMD capacitor. It still has some CPU activity but it is not working and won't boot the computer. I gotta get that fixed but I don't know the value of the capacitor (they literally broke to dust). I looked at my working AdSpeed and the resistor is 221 but I can't make out the markings on the cap. I should probably start a new thread on that but just in case someones expert eyes can tell what this is...
IMG_1904.jpeg
Undamaged one
IMG_1899.jpeg
Damaged one

Maybe having an oscilloscope would help when I clumsily break $hit.
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H5C1, H5C5B, 1040 ST, Mega ST, STe, Mega STe, Falcon, TT030, Amiga 2k V2+, Amiga 2k Video Toaster GVP030, Amiga 500, Amiga 500+ V2, Amiga 500+ Firebird V4, Amiga 1200 PiStorm, FPGA: V4SA, MiST, MiSTer, UnAmiga, U64 Elite
ijor
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Re: officer960's H5 C1 build

Post by ijor »

I haven't been following this thread and I'm afraid I don't have time now to read it from the beginning. Just a couple of comments that might not be fully relevant.

I doubt that a small delay on the CPU clock would break syncscroll. If it does, it shouldn't affect only syncroll. At the minimum you should see a difference on the regular benchmarks.

As I told you already, IMP chipset on the H5 (or H4) it is probably not a good idea, or at least it would be natural to expect problems. Even on an original ST, there is some stuff that doesn't work with IMP chipset.

Why are you using precisely Enchanted Land for testing? It uses non standard syncscroll techniques (it actually has a bug and almost works just by chance). I can't say I'm 100% sure, I tested Enchaned Land long ago, but I think it doesn't depend on WS.

A better test for WS compatibility is, of course, Closure. But be aware that Closure also depends on the SHIFTER wakeup (that's a different type of wakeup, and it can't be measured programmatically).
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com
officer960
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Re: officer960's H5 C1 build

Post by officer960 »

ijor wrote: 14 Aug 2025 03:45 I haven't been following this thread and I'm afraid I don't have time now to read it from the beginning. Just a couple of comments that might not be fully relevant.

I doubt that a small delay on the CPU clock would break syncscroll. If it does, it shouldn't affect only syncroll. At the minimum you should see a difference on the regular benchmarks.

As I told you already, IMP chipset on the H5 (or H4) it is probably not a good idea, or at least it would be natural to expect problems. Even on an original ST, there is some stuff that doesn't work with IMP chipset.

Why are you using precisely Enchanted Land for testing? It uses non standard syncscroll techniques (it actually has a bug and almost works just by chance). I can't say I'm 100% sure, I tested Enchaned Land long ago, but I think it doesn't depend on WS.

A better test for WS compatibility is, of course, Closure. But be aware that Closure also depends on the SHIFTER wakeup (that's a different type of wakeup, and it can't be measured programmatically).
Thanks @ijor. Why Enchanted Land? It worked on one machine but not another and it uses obviously weird syncscroll - my probably incorrect thought process was if it could handle that game and a couple demos with some full screen scrolling they’d be decent tests. I’ll certainly try Closure and anything else you suggest.

Regarding the IMP chipsets - I used those because they were in non-working ST’s AND almost all of the ST’s I have are IMP chipsets (except the one I assembled the C5B with and it had a bad DMA). I’ll be trying to source other chipsets just don’t want to kill working ST’s if I don’t have to.
H5C1, H5C5B, 1040 ST, Mega ST, STe, Mega STe, Falcon, TT030, Amiga 2k V2+, Amiga 2k Video Toaster GVP030, Amiga 500, Amiga 500+ V2, Amiga 500+ Firebird V4, Amiga 1200 PiStorm, FPGA: V4SA, MiST, MiSTer, UnAmiga, U64 Elite
officer960
Posts: 67
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Re: officer960's H5 C1 build

Post by officer960 »

Ran "Closure" by SYNC on both of my H5's. There are observable differences in graphics (maybe not with my poor recording techniques :lol: ) which is to be expected. Anyway the videos are below if anyone cares and I've found this interesting as I had never known anything about WS. I just always attributed glitchy software to it being an "Atari thing".

H5 rev C1 (WS3) Config: IMP Shifter C070713-002, IMP DMA C100110-001, IMP MMU C100109-001, IMP GLUE C070714-001 (all 1987 Date Codes), PLCC 68HC000EI20, Exxos Booster configured as ROM Decoder/Booster Disabled. RGBtoHDMI, Closure by SYNC run on a Gotek Drive

H5 rev C1 Closure by SYNC

H5 rev C5B (WS2) Config: Shifter C025914-38A, DMA C025913-38, MMU C025912-38, GLUE C025915-38A, AdSpeed set at 8MHz, RGBtoHDMI, Closure by SYNC run on a Gotek Drive

H5 rev C5B Closure by SYNC
H5C1, H5C5B, 1040 ST, Mega ST, STe, Mega STe, Falcon, TT030, Amiga 2k V2+, Amiga 2k Video Toaster GVP030, Amiga 500, Amiga 500+ V2, Amiga 500+ Firebird V4, Amiga 1200 PiStorm, FPGA: V4SA, MiST, MiSTer, UnAmiga, U64 Elite
ijor
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Re: officer960's H5 C1 build

Post by ijor »

officer960 wrote: 14 Aug 2025 04:19 Regarding the IMP chipsets - I used those because they were in non-working ST’s AND almost all of the ST’s I have are IMP chipsets (except the one I assembled the C5B with and it had a bad DMA).
That's understandable, of course. But don't expect much help from us if this is causing any problems or incompatibilities. Because as said, we don't have much experience with the IMP chipset on the H5. And because some stuff is actually expected to fail when running on IMP chipset.
http://github.com/ijor/fx68k 68000 cycle exact FPGA core
FX CAST Cycle Accurate Atari ST core
http://pasti.fxatari.com

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