CURRENT SCHEMATIC

All information relating to the Alpha plus all the WIP threads etc.
User avatar
exxos
Site Admin
Site Admin
Posts: 28377
Joined: 16 Aug 2017 23:19
Location: UK

CURRENT SCHEMATIC

Post by exxos »

This is the current schematic for the new STF design.

This still needs checking against the STFM schematic for mistakes.

STF-min.png

Also see here https://www.exxosforum.co.uk/forum/viewt ... ?f=19&t=15 as the RS232 circuit has been replaced totally.
You do not have the required permissions to view the files attached to this post.
User avatar
tfhh
Posts: 24
Joined: 26 Aug 2017 17:31
Location: Germany

Re: CURRENT SCHEMATIC

Post by tfhh »

Hi,
exxos wrote: 05 Sep 2017 16:39 This is the current schematic for the new STF design.
This still needs checking against the STFM schematic for mistakes.
Looks very cool. And I see, you´re also a friend of Eagle :)

Jurgen
User avatar
IngoQ
Site Admin
Site Admin
Posts: 1074
Joined: 22 Aug 2017 08:38
Location: Germany

Re: CURRENT SCHEMATIC

Post by IngoQ »

:shock: Wow... :)
Ingo :geek:

| Atari 1040STE@32MHz | Amiga 1200 (ACA1220) | Atari 800XL (U1MB, SIDE2) | Atari 130XL (Sophia DVI) | C64 (1541 Ultimate II, Rev3 RFMod Replacement) | TI 99/4A (F18A, 32k, FlashROM 99) | Sinclair ZX Spectrum 128 (Stereo, DivMMC) | Amstrad CPC664 (512k, M4 Wifi) | ... |
keli
Posts: 97
Joined: 22 Aug 2017 13:34

Re: CURRENT SCHEMATIC

Post by keli »

How does the RAM circuit select between the upper and lower half of its 32 bit data bus? I looks like you've just connected each pin of the 16 bit bus twice.
User avatar
exxos
Site Admin
Site Admin
Posts: 28377
Joined: 16 Aug 2017 23:19
Location: UK

Re: CURRENT SCHEMATIC

Post by exxos »

keli wrote: 06 Sep 2017 12:53 How does the RAM circuit select between the upper and lower half of its 32 bit data bus? I looks like you've just connected each pin of the 16 bit bus twice.
Connects up the same as a 4 MB 72 pin simm.
keli
Posts: 97
Joined: 22 Aug 2017 13:34

Re: CURRENT SCHEMATIC

Post by keli »

exxos wrote: 06 Sep 2017 16:27 Connects up the same as a 4 MB 72 pin simm.
Yeah, I never understood those hacks either. I see you used to have a 72 pin SIMM kit available as well (and I think I might have asked a similar question before.) If I'm not completely wrong, 72 pin SIMMs do not have ways to target individual bytes. How does updating or reading either one (only CASxLow or CASxHigh asserted) or even two bytes out of available four bytes work?

Since you've produced the 72pin SIMM kits I don't doubt it works, I just can't understand exactly how it works :)
keli
Posts: 97
Joined: 22 Aug 2017 13:34

Re: CURRENT SCHEMATIC

Post by keli »

I think I get what I had wrong. The pinout on pinouts.ru is different. It has A10 and A11 where other pinouts list CAS2 and CAS3.

Mystery solved! :)

Edit That previous pinout was something called "72pin simm with ECC". It's not the first time I've been fooled by the wrong diagram. The correct pinout for a 72 pin simm is: http://pinouts.ru/Memory/Simm72_pinout.shtml
User avatar
exxos
Site Admin
Site Admin
Posts: 28377
Joined: 16 Aug 2017 23:19
Location: UK

Re: CURRENT SCHEMATIC

Post by exxos »

Yeah, I use that site mostly. I have seen sites with wrong pinouts. But IIRC, there are some simms used in some odd PC's which do have odd pinouts.

Return to “ALPHA DEVELOPMENT INFO”

Who is online

Users browsing this forum: ClaudeBot and 6 guests