exxos's Atari, Amiga & retro forum

Thank you. What puzzles me is the mechanism that would converts the HSYNC source pulses into serrated CSYNC pulses when VSYNC is low.

sporniket wrote: 15 Nov 2020 16:11 Thank you. What puzzles me is the mechanism that would converts the HSYNC source pulses into serrated CSYNC pulses when VSYNC is low.

Its just a simple logic.. If vsync or hysnc is low then csync is low. Its still a composite signal format, just its missing RGB information.

exxos wrote: 15 Nov 2020 16:15

sporniket wrote: 15 Nov 2020 16:11 Thank you. What puzzles me is the mechanism that would converts the HSYNC source pulses into serrated CSYNC pulses when VSYNC is low.

Its just a simple logic.. If vsync or hysnc is low then csync is low. Its still a composite signal format, just its missing RGB information.

Thank you.

Looked at this old thread at Atari-Forum? The link goes directly to the circuit they use to combine HS and VS. They use 2 XOR gates in a 74LS86 to solve the problem.

But creating schematics and doing small PCB is nevertheless a fun project.

Still really needs a driver transistor as logic might not output enough current if its 75R terminated .

Even so a simple 2 input AND gate would do the same job. If either input is low then the output is low.

DoG wrote: 15 Nov 2020 18:30 Looked at this old thread at Atari-Forum? The link goes directly to the circuit they use to combine HS and VS. They use 2 XOR gates in a 74LS86 to solve the problem.

Yes I also found this schematics when doing research. I will also do a version using that.

DoG wrote: 15 Nov 2020 18:30 But creating schematics and doing small PCB is nevertheless a fun project.

yes.

exxos wrote: 15 Nov 2020 18:34 Still really needs a driver transistor as logic might not output enough current if its 75R terminated .

Even so a simple 2 input AND gate would do the same job. If either input is low then the output is low.

Thanks for the advices.

Today I got the donor machine for the H5 build, now eagerly waiting the remaining parts (I believe that my H5 seems to be in the customs office for now since the 27, because it is still at Roissy CDG airport...).

Anyway I did a little check-up... one disassemble/reassemble cycle... And then the faithful diagnostic cartridge Checked the RAM, the Color and the OS, only the latter seems to have problem. I don't mind given that the ROM will not be of use. I noticed that the video is quite noisy. It's a little bit noticiable at 60Hz (the slight embossing effect on the right) And more noticiable (and moving) at 50Hz So, the PSU of this machine will no get near my H5 build...

On the schematic front, and my script to generate Kicad symbols from structured Markdown datasheets of an arbitrary IC.

I was pondering about generating big custom ICs as multi-unit symbols in kicad in order to create schematics focused on a group of signals (say, the distribution of the clock signals), and took the time to implement that.

Then I created the source datasheet for the GSTMCU of the STE (the page of info-coach was extremelly helpfull for that). And it is so huge that I would need to setup an A3 sized page to accomodate the symbol. So I feel right about splitting big ICs. Next step will be to create a POC of schematics with a few more ICs to assess the readability and the understandability of the resulting document.

for the curious, here are a sample sheets demonstrating the blitter and the gstmcu as single unit vs multi unit.
And this is the generated libraries that are used in this demo : By the way, while drawing the schematics, the subtext describing the unit is not visible, I don't know how to show it. Fortunately, it is visible on the printed/plotted schema.

I must have mentionned it before, but the source project is here : https://github.com/sporniket/retro-comp ... schematics

Got my H5 B1 this morning, still waiting my last order of IC sockets that exxos shipped recently, then I will be able to start my build.