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Falcon clock buffer patch V2 progress

Posted: 18 Mar 2019 11:49
by exxos
Started a new thread as its not relevant as such to the topic below which isn't a "progress thread"..

https://www.exxosforum.co.uk/forum/viewt ... ?f=17&t=84

Anyway, just stating the PCB's have arrived today. I'm busy with the 4MB boards this week, but will try and build a couple of these clock boards up next week for stock.

I have tested the changes on my own falcon and it seems fine. Though this V2 does help solve some screwy issues on the SDMA clock. So this may help with people with bus speeders over the V1 design.

How it looks, is that the clock doesn't reach zero volts properly and the heavy loading on the clock and / or voltage dividers seems to just get around the issue by lowering the voltage. The logic low level seems to only happen with undershoot (such as its the logic low level is more like 1V and undershoots to -1V for example, so there isn't a proper logic low level there.) So I have re-biased the signal so the low level is actually low now. The overall voltage on the clock still remains around 4V (was more like 2V with other patches). The signal looks fine on my scope to me so thats I can do until someone with a speeder tries it and and helps to debug any further issues. The resistors on the board have been lowered to cope with faster clock speeds also. I have also added a solder jumper which will route the SDAM clock via 2 more inverters as this seems to be a theme with some patches also.


IMG_3867.JPG

Re: Falcon clock buffer patch V2 progress

Posted: 18 Mar 2019 12:37
by Steve
Is the installation process the same as with the old model?

Re: Falcon clock buffer patch V2 progress

Posted: 18 Mar 2019 12:38
by exxos
Steve wrote: 18 Mar 2019 12:37 Is the installation process the same as with the old model?
Yep. fitting wise identical.

Re: Falcon clock buffer patch V2 progress

Posted: 21 Mar 2019 12:53
by exxos
Built up a board for testing..

v2.jpg

I've had to put back the 100R on the input, it was ringing up and down 2 volts above and below 5V!

IMG_3893.JPG

I will try and build up a couple myself to get them back into stock. Though the rest will be sent off to be assembled as I haven't got time to build up the things myself.

Re: Falcon clock buffer patch V2 progress

Posted: 29 Mar 2019 15:11
by exxos
About 100 of the V2 buffer boards have been assembled. I need to bag them up for store stock next which will take a couple days. There is still a couple currently in store anyway.

I have also designed a V3, which I don't plan for production. Though this version will mimic the delay of the phantom's patches extra logic inverter. As its unknown if its a bad signal (which is patched better in V2) or it needs a longer delay for the SDMA I don't know. The V3 will be around in a few weeks time if anyone wants to try it out.

Re: Falcon clock buffer patch V2 progress

Posted: 22 Sep 2020 00:02
by Badwolf
Hi Exxos,

Here's a glamour shot of my patch install. Works a treat.

Thanks for putting it together and the next day(!) delivery :D

:cheers:
BW

IMG_3814.jpeg

Re: Falcon clock buffer patch V2 progress

Posted: 22 Sep 2020 00:03
by exxos
:bravo: :goodpost:

Re: Falcon clock buffer patch V2 progress

Posted: 28 Dec 2020 14:18
by Steve
Hey @exxos ,

You mentioned having a V3 board available to test. Since I have a Phantom patch could I test it out for stability? My sdma clock is cut and wired directly to the Phantom clock patch, can I wire this up directly to your V3 to avoid having to re-patch the motherboard?

Re: Falcon clock buffer patch V2 progress

Posted: 28 Dec 2020 14:43
by exxos
@Steve The ones in my store now are actually V3. The solder pad turns on/off a 3 gate delay which should simulate the delays of the second chip on phantom. As to if the delay is long enough.. In theory it should be the same.. but of course I have no way to test or debug.

Capture.PNG

Re: Falcon clock buffer patch V2 progress

Posted: 29 Dec 2020 12:39
by Steve
Ah okay, so I guess I could install it and try with that on/off to see if it makes any stability differences. Any thought on my sdma clock wire?