Falcon clock buffer patch V2 progress
Posted: 18 Mar 2019 11:49
Started a new thread as its not relevant as such to the topic below which isn't a "progress thread"..
https://www.exxosforum.co.uk/forum/viewt ... ?f=17&t=84
Anyway, just stating the PCB's have arrived today. I'm busy with the 4MB boards this week, but will try and build a couple of these clock boards up next week for stock.
I have tested the changes on my own falcon and it seems fine. Though this V2 does help solve some screwy issues on the SDMA clock. So this may help with people with bus speeders over the V1 design.
How it looks, is that the clock doesn't reach zero volts properly and the heavy loading on the clock and / or voltage dividers seems to just get around the issue by lowering the voltage. The logic low level seems to only happen with undershoot (such as its the logic low level is more like 1V and undershoots to -1V for example, so there isn't a proper logic low level there.) So I have re-biased the signal so the low level is actually low now. The overall voltage on the clock still remains around 4V (was more like 2V with other patches). The signal looks fine on my scope to me so thats I can do until someone with a speeder tries it and and helps to debug any further issues. The resistors on the board have been lowered to cope with faster clock speeds also. I have also added a solder jumper which will route the SDAM clock via 2 more inverters as this seems to be a theme with some patches also.
https://www.exxosforum.co.uk/forum/viewt ... ?f=17&t=84
Anyway, just stating the PCB's have arrived today. I'm busy with the 4MB boards this week, but will try and build a couple of these clock boards up next week for stock.
I have tested the changes on my own falcon and it seems fine. Though this V2 does help solve some screwy issues on the SDMA clock. So this may help with people with bus speeders over the V1 design.
How it looks, is that the clock doesn't reach zero volts properly and the heavy loading on the clock and / or voltage dividers seems to just get around the issue by lowering the voltage. The logic low level seems to only happen with undershoot (such as its the logic low level is more like 1V and undershoots to -1V for example, so there isn't a proper logic low level there.) So I have re-biased the signal so the low level is actually low now. The overall voltage on the clock still remains around 4V (was more like 2V with other patches). The signal looks fine on my scope to me so thats I can do until someone with a speeder tries it and and helps to debug any further issues. The resistors on the board have been lowered to cope with faster clock speeds also. I have also added a solder jumper which will route the SDAM clock via 2 more inverters as this seems to be a theme with some patches also.