exxos's Atari, Amiga & retro forum

So really this machine is a build by people who dont know anything about MSX machines.

terriblefire wrote: 30 Sep 2021 16:53 So really this machine is a build by people who dont know anything about MSX machines.

Good. Opportunity to learn something new :)

I am investigating increasing performance of F722 chip.
I am at 250-300ns between trigger and first response of microcontroller, but there is another trick which I can try, and see if it make any difference.
Move ISR vector table and interrupt code to ITCM RAM, 16k ram designed to do exactly that this section is CPU accessible only, and no wait states at all. I might need to squeeze main as well there, and any few other bits if space allows, there is special DTCM RAM section for data fast access as well which is designed for very fast access as well. I might think how to use it for my advantage as well.
Issue is I never done it before, so I need to learn how to write liner script, and startup routines, but I have some examples from ST, so I should manage.

Main and EXTI15_10_IRQHandler in memory in ITCMRAM space
ISR Vector still in Flash ITCMFlash space


WIth TCM acceleration and prefetch on.


Next step, move ISR Vector Table to RAM. Still may shave few cycles, but it will take me some time to actually crack this one. Don't know how to modify liner. I understand general idea of LDs, but this one is much more complex as thought.

I am hoping for close to 100ns as possible.

And with ISR Vector Table in RAM (works only one before crashing.... but I know now that I need to fight for it)


EDIT:
I couldn't replicate the last one below 100ns, but consistently is 120-150ns. Good enough, I will have 100ns to reprogram gpio, and pull data from RAM (via fast bus) and bail off in next 100-200ns.

I think 200ns to 300ns is more than enough for the MSX.

Do we know if internally IO has this wait state TW as well?

I'm not sure the primary slot actually has the WAIT state. Its optional i think?

WAIT is controlled by the CPLD so we can wait.

I have optimised a little bit more by moving some more utils stuff to ram, and tested how to time small amount of time, and simple NOP loop does the job. It is literally all possible performance optimisations which can be done on stm32f7.

I have set up 192k of SRAM as well, just for .data if it was needed for transferring some bigger stuff.

Well depending on how well this all works we might be able to ditch the EPROM and save a few £££.