exxos wrote: 02 Jan 2026 12:03
ijor wrote: 02 Jan 2026 02:52
I would say, as I always say when dealing with CPLD or FPGA code, a comprehensive timing analysis is extremely important.
I think the problem is that the SDRAM data is not ready when the CPU tries to latch it.
That's perfectly possible, and even likely. I'm certainly not surprised. And that's precisely why timing analysis is so important.
Slowing the cycle by 20ns works, as the CPU doesn't latch too early when the data isn't quite stable yet. But of course that is a significant shift for data hold on the SDRAM as well. It works.. Though it slows down TTram access.. Because the CPU is effectively missed 2 sampling edges. So now I just delay by 10ns. It misses the first edge, latches on the second. The result is it is now stable with not much of a performance hit.
There is nothing intrinsically wrong with this approach, but you must be careful. You are explicitly relying on the data arriving late. But what if the data if not arriving late in some circumstances? Say, somebody might use a slightly faster RAM chip, some CPLDs could be slightly faster (even with the same speed grade). If the data happens to not arrive late, the CPU would be latching too late (or if you want, data would be too early, same thing).
You must make sure that data would always be "late", which is not so easy to confirm. Or otherwise you can issue two identical RAM read commands in a row. This way the CPU would always latch the correct data even if it happens to not be late. If the data is late (the hardware is slow), the CPU would latch the first iteration. If it's early (hardware is faster), it would latch the second one. But note that issuing two read commands would extend the SDRAM state machine one extra cycle, which might be a problem.
That is probably why the AI treats it as meta stability, because its not really wrong about latching on a edge which is changing.
No, that's not what AI is saying at all. According to what you posted earlier, AI is saying that the CPLD state machine could have a synchronization problem. AI is talking about how the CPLD handles the control signals coming from the CPU. No relation with the data going from the SDRAM to the CPU.
But the thing is, that was the conclusion to a very long conversation where I was using the AI as my "rubber duck" in all this to come up with ideas on things to look for.. I probably would have never considered a lot of stuff if it wasn't for AI suggestions. Whether it's talking total BS or not, it is greatly helped with a lot of issues and indeed even talked about SDRAM timings a lot where a lot of things wasn't considered.
Yes, I agree. The AI could give useful hints and ideas. As long as you are aware that it is not authoritative and anything that the AI claims should be doubled checked and confirmed, yes, it could certainly be useful.
But again, the AI probably failed in not giving you the most valuable recommendation. Perform a timing analysis. Or at least it wasn't mentioned in the AI quote you posted.
Been going over night..
Fabulous! :)