The LaST Upgrade Part 39 - ST536 030 ACCELERATOR

Last updated April 7, 2026

 

ST536 144XL PLD (obsolete)

The ST536 REV5 ST EDITION is ST accelerator which offers 50Mhz 030 CPU with 64MB fast-ram and IDE.

The firmware & hardware has been extensively revised to better suit the Atari ST range of computers. The PCB has been revised in various places to include more parts on the bottom so that they can be supplied preassembled. It's most prominent new feature is the on-board DUALTOS ROM where the decoding is built into the PLD. You can for example have TOS206 and EMUTOS in ROM without requiring a separate dual TOS board. There have been other tweaks for better compatibility with the Atari machines such as fixing the IDE port to use a standard cable.

Please see the forum for all related development progress. https://exxosforum.co.uk/forum/viewforum.php?f=94

 

TOS206 NO BLITTER BENCHMARK
TOS206 BENCHMARK WITH BLITTER

ST536 TOS WITH MAPROM &BLITTER

Some scores are slower due to ST-RAM caches being enabled (less cache hits for alt-ram). Software running in ST-RAM should benifit from the ST-RAM caches being enabled.

ST536 TOS WITH MAPROM & NVDI
FIRMWARE & TOOLS (144XL PLD VERSION)

LATEST 144XL FIRMWARE

TOS206 & EMUTOS 2025 RELEASE (UK - ENGLISH)

REV5_ST526_SLOW_ROM V2 September 19 2022, FIRMWARE & MAPROM

EXPERIMENTAL FIRMWARE - Cache experimentation firmware- untested. 13 December 2022

ST536 TOS206 v2 - March 5, 2023 - Exxos patched TOS206 for the ST536 only - Alpha V2 release. TTram fix. Untested- All languages.

 

OLD / OBSOLETE FIRMWARE:

REV5 ST536 April 25, 2022 - Offical final release.

ST536 TOS206 May 16, 2022 - Exxos patched TOS206 for the ST536 only. Alpha release.

REV5_ST526_SLOW_ROM September 15, 2022 - Will alow 120ns ROM to be used. Also fixed a small blitter busgrant issue on original machines. Caches enabled in firmware.

REV5 ST536v2_IDE_AB April 19, 2022 - IDE autoboot

REV5 ST536Av2 April 15, 2022 - IDE Enabled

REV5 ST536r5A2 - 07/04/2022 - ALPHAv2 - No IDE & blitter- Clock switching - Only 50MHz on alt-ram (same as original TF536 firmware). Trying to fix HDD issues.

REV 3 & 5 ALPHA FIRMWARE VST2A 288XL (IDE not supported, blitter will malfunction) H4 / STF (288XL no longer supported)

REV 3 & 5 ALPHA FIRMWARE VST2A 144XL (IDE not supported, blitter will malfunction) - STE build

REV 3 & 5 ALPHA FIRMWARE VST2A 144XL (IDE not supported, blitter will malfunction) - H4 / STF

FASTROM - will load the TOS206 image into fastram and reboot and then goto desktop. Includes YAARTTT & PRGFLAGS.

MAPROM 1.8E - Exxos edit, to turn off "copy lower RAM varibles to fast ram" as it would corrupt the floppy contents. Will copy ROM to FAST-RAM. (seems lower than FASTROM?!)

MAPROM SOURCES - Home of MAPROM tools.

 

 

KNOWN ISSUES / OTHER INFO (144XL PLD VERSION)

Blitter must be removed for EMUTOS. EMUTOS has not been tested with later ST536 builds and may malfunction.

Caches must be off if using original TOS206. Please use ST536 TOS206 and official software on this page instead as it fixes the cache issues in TOS206. Graphics corruption will happen if you're using anything else but the 4K version of MAPROM_C. In particular when using the blitter. BLTFIX must be used if using the blitter.

ST536 TTram test is slower than the PAK030 due to 16bit ROM access. Whereas PAK030 has 32bit ROM. Also 16bit ROM access was slowed to allow slower EPROMs to be used. MAPROM should be used to allow ROM to be copied into TTram for maximum ROM performance. The ST536 ROM is only there to "get you booting".

ASCI wire is no longer required in the latest firmware. It may cause DMA issues if used otherwise.

ST536 TOS startup messages remain in English. Desktop should be in what ever language you chose for your ROM.

Sometimes during start-up, in particularly after just flashing the firmware or resetting the computer, it may display a message "BAD ROM CHIP IN E". Currently I am not sure why this happens but the solution is to turn the computer off for 30 seconds and power up so TOS correctly recognises a cold reset. The screen will turn green to indicate TOS did a proper "cold boot".

 

PARTS LIST (144XL PLD VERSION)

PLD - XC95144XL-10TQ144C (10ns)

SDRAM - W9825G6KH-5 (WINBOND) or AS4C16M16SA-6TCN (preffered)

BUFFERS - SN74CB3T3245PW

PGA SOCKET - https://www.exxoshost.co.uk/atari/store2/#0181

REV 3 PCB - https://www.exxoshost.co.uk/atari/store2/#0220

MC68030RC - https://www.exxoshost.co.uk/atari/store2/#0187

TOS206 ROM - https://www.exxoshost.co.uk/atari/store2/#0143

100MHz OSC (rev 3 only) CB3LV-3C-100M0000

2025 NEWS

The original ST536 (with 144XL PLD) was discontinued due to lack of demand and no longer supported. You can likely retrofit older versions by upgrading the to a 288XL 6ns PLD.

But I am now working on a new improved design which is based upon the STE536. You can find progress on the new ST536 HERE.

 

TOS206 MODS

My patched TOS206 fixed cache issues with the 030 CPU which will corrupt DMA activities. It will auto copy TOS ROM to TTram in a reserved block of TTram above the 60MB mark. It will survive a warm reset but (at the time of typing) a cold boot seems to cause a "bad rom chip error", I don't know why. If you get that, power down for 10 seconds and reboot.

Cache and blitter options are available in the desktop menu. These are saved into unused bits in newdesk.inf. TTram test after STram test will also show if you don't skip STram test on powerup.

 

ST536 2025 REV >5.50

Revision 5.50 now uses the 288XL 6ns PLD and all older firmware & software from previous runs are not compatible with this updated 5.50 revision.

TOS206 patched can be obtained from the STE536 page HERE.

BETA "Birdseed boards" can be purchased HERE.

NOTE: Only 60MB of TTram is available as some is used for ROM shadow. Typically 60MB is free to use, the next 1MB is a "black hole" to prevent TOS from declaring it. Then ROM area and special registers. RAM could be used above that in special software but probably nothing will use it.

 

JUMPERS

JTAG - PLD programming header.
CDIS - CPU Cache disable (generally not used)
MMUDIS - CPU MMU disable (generally not used)

ROM HEADER:
BANK 0 - Lower ROM bank select
BANK 1 - Upper ROM bank select
512K ROM - Can use 512K OS ROM (currently not used)

ACSI10 - No longer used - DO NOT CONNECT

ROM_CE - Aux output ROM decoding signal - DO NOT CONNECT.

PWR2 - 5V power output - Can be used to power a external fan etc ( generally not used)

Any other jumpers or solder pads are not to be used or connected.

 

MODIFICATIONS - All 2025 versions <5.60

Do the modifications below.

NOTE if you have a original Atari PSU such as SR98, you need to recap and alter the voltage to about 5.30V.

While these mods can be done to the older < 5.60 boards, as they are a few versions behind now, I consider them obsolete and unsupported. Version 5.62+ arethe current minimum supported board.

 

Solder a 330R resistor on the bottom of the CPU socket as shown above. This adds termination to the CPU clock.

 

Solder a thick wire , keep a short as possible, between the points illustrated by the red arrows. This firms up the 3.3V rail reducing noise.

 

Solder a 4.7nF 0603 capacitor across every small cap on the bottom of the PCB.

The 3 caps above R6 need not be done. The 3 large caps C8,C6,C9,C3 can be left. C33 *should* be fitted but might be missing on some boards. Solder a 4.7nF there if missing.

These mods improve the transient response of the 3.3V rail.

 

Below we need to cut a track to the CPU clock and fit in a 68R resistor (boards over revision 5.60 already have this mod) . This solves a lot of stability issues.

 

Scrape the solder resist (grey) very carefully off the slightly larger track near the PLD . CUT the track near the CPU (yellow). Solder a 68R between the scraped track near the PLD to the PGA clock pin as shown.

If you have a resistor or capacitor already on the bottom of the PCB, on the CPU clock, remove both.

Remove the 4 resistor packs in a row on the bottom of the PCB between the CPU and ROM. See image HERE

Below carefully scrape away the copper resist and cut the track..

 

Then solder a 68 0603 resistor across the cut track.

This is a STERM fix as it has very bad ringing and can cause TTram to glitch.

Scrape the solder resist off the three tracks as below and then make a cut to isolate them..

 

Then solder a 33R 0603 (not 47 as shown in the image) across the three broken tracks. this soul is bad ringing on memory RAS/CAS lines.

 

 

BGACK needs a 1K pullup from (68K DIP) pin 12 (BGACK) to pin 14 (VCC 5V).

(other mods likely to follow soon)

 

 

MODIFICATIONS - REV 5.62

Blob over the solder jumpers as shown.

BOTTOM OF PCB

2 small SMT regulators as shown need a small wire to fix power on issue.

Similar wire on top of the board regulator. Red wire shows link.

 

 
288XL FIRMWARE

V3F BETA FIRMWARE - March 24, 2026 - IDE AB disabled - blitter untested.

V4C2 FIRMWARE April 7, 2026

 

 

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