Re: The TF330 is here
Posted: 26 Nov 2018 22:35
reading this i remember same issues here on german side, no chances to run a card with @25Mhz using 64MB SDRAM expansion.. may be same reason... :?
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Yeah. 21Mhz was the lower limit for the TF530 with how I wired it up. Makes sense that this one is 42Mhz with everything x2.exxos wrote: 26 Nov 2018 22:20If your trying to fit 2 fast cycles inside a slower one, thats probably why slower speeds are not working. I half recall you talking to me about this before ? I think you was trying to run fast-ram cycles at the same time as "MB" cycles were happening ?terriblefire wrote: 26 Nov 2018 22:12 I agree. I've just found the CD32 very picky on this. Its actually been quite easy to get 50Mhz working. 25Mhz is not happy at all. I think its because 14.8Mhz and 25Mhz are too close together. You cant fit 2 fast cycles inside one slow cycle. Perhaps I should just fit an 80Mhz crystal instead and go with 40Mhz and be done with it.
EDIT: Amiga's dont do ARB and slow down BTW. They cycle overlap and crash. its a real PITA.
Even so, if clocks are out of sync its complicating matters as that fast clock timing is going to be a bit "hit and miss" in the lower clock domains timing.
EDIT: You probably would need a fast domain clock, I would guess 2.5 or 3x faster than the 14MHz clock to do 2 fast cycles inside a slower one. Probably like 42MHz would be needed to complete 2 full clocks reliable inside a 14MHz clocked cycle.
Indeed. I may just give be up and use the 28mhz signal for slow running. The CPLD is already very full with the SDRAM code.exxos wrote: 27 Nov 2018 08:35 You might be making things worse adding a delay. I mean 25MHz is 40ns cycle time. So you can be 40ns faster or slower than whatever you are timing it to. So adding 70ns would mean you will be 40ns+70ns = 110ns later than your expecting depending on where the cycles happen to align up.
The PLL multiplier I tried was responding to noise and upsetting the PLL frequency. So while it worked 99% of the time just fine, it was causing random crashes as the "locked on frequency" changed... IMHO that kinda defeats the object of a PLL if it adjusts to the input frequency in real time :roll: A PLL should lock onto a signal and bloody well stop there, but I haven't found one which actually does that.. In the end I gave up screwing around with them. I probably documented all this "*somewhere* .terriblefire wrote: 27 Nov 2018 13:41 I was but when Chris and I tried a clock multiplier there was an issue.. can’t remember that it was now.
This one does this task excellent:terriblefire wrote: 27 Nov 2018 13:41 I was but when Chris and I tried a clock multiplier there was an issue.. can’t remember that it was now.