Re: exxos IDE interface (untested)
Posted: 17 Jan 2019 15:46
I am slightly confused over the CS0 and CS1 signals which are linked to A5.
According to the ATA spec, they are used to select upper or lower 8bit bank select in the drive. Fair enough.. but the CPU has a 16bit bus, so why doesn't the data transfer as a 16bit block ?!
The CPU would actually have to do 2 bus cycles I assume to change the A5 for upper and lower 8bits ? Would seem a bit pointless having a 16bit drive and interface, and yet its looking like its driven as a 8bit device :shrug:
EDIT:
I think half the confusion is coming from this site...
http://blog.retroleum.co.uk/electronics ... interface/
It says
EDIT2:
OK http://citeseerx.ist.psu.edu/viewdoc/do ... 1&type=pdf
According to the ATA spec, they are used to select upper or lower 8bit bank select in the drive. Fair enough.. but the CPU has a 16bit bus, so why doesn't the data transfer as a 16bit block ?!
The CPU would actually have to do 2 bus cycles I assume to change the A5 for upper and lower 8bits ? Would seem a bit pointless having a 16bit drive and interface, and yet its looking like its driven as a 8bit device :shrug:
EDIT:
I think half the confusion is coming from this site...
http://blog.retroleum.co.uk/electronics ... interface/
It says
Then later says.When /CS0 goes low, registers 0-7 are accessed, and when /CS1 goes low 8-15 are accessed.
So I am assuming the transfer is actually 16bit and CS1 may not actually get used for anything...Tip: You typically dont need to access IDE registers 8 to 15 so /CS1 can just be pulled high via a resistor.
EDIT2:
OK http://citeseerx.ist.psu.edu/viewdoc/do ... 1&type=pdf
Why couldn't some site or document have actually just said that :roll:Chip Select (CS0:1) - Selects the command block or control block registers.