Re: Falcon Clock Patch V5 series
Posted: 22 Sep 2024 14:00
Does anything changes if you change the STram board ? Can you run ST RAM test on the unstable machine setups ? No idea if your trying to boot from SCSI or IDE ? Maybe experiment as IDE being connected to the bus without buffering isn''t ideal.
Other than the SDMA timings which I don't know if relevant with the blitter on the falcon, I can only suggest patching some 10K SILs across the falcon databus (maybe also address) and see if it helps.
I emailed Mr Zcuba about it all. Basically he says the 030 CPU, CT60 clock timing isn't that important. He suspects the SDMA clock might be timing critical. But he did't look into it more.
As to if that timing can cause CT60 related issues, no idea. I assume it just causes audio drive issues as it does in 030 mode. BUT, with it being a DMA device, maybe floppy polling is enough to cause conflicts with the blitter with it also being a bus master ? I really cannot say and would be a rabbit-hole type problem I think to diagnose.
I tried the new V5 and the SDMA clock is in perfect sync with combel now. BUT, a under-sight was when the CT60 is removed, it changes the timing again. So I have done a new design with a fixed delay rather than syncing to the EXP clock.
Sync can be taken from the SDMA pin directly, but its adding another wire.. which will add another delay anyway. So I think having a fixed timing is likely the best solution. However, as this is all a turned circuit. Every falcon is likely different.. So even with a PLL, obtaining a perfect sync isn't simple. You have a 4ns delay tot he SDMA, so a direct wire may have 2ns for the feedback. So there is no point in trying to compensate for 2 delays which will have random timings anyway.
But even so, I am skeptical the clock sync with the SDMA is the root cause of peoples CT60 issues. I have had various timings on mine and never seen any hard crashing. So I personally would lean more towards bus stability issues.
Other than the SDMA timings which I don't know if relevant with the blitter on the falcon, I can only suggest patching some 10K SILs across the falcon databus (maybe also address) and see if it helps.
I emailed Mr Zcuba about it all. Basically he says the 030 CPU, CT60 clock timing isn't that important. He suspects the SDMA clock might be timing critical. But he did't look into it more.
As to if that timing can cause CT60 related issues, no idea. I assume it just causes audio drive issues as it does in 030 mode. BUT, with it being a DMA device, maybe floppy polling is enough to cause conflicts with the blitter with it also being a bus master ? I really cannot say and would be a rabbit-hole type problem I think to diagnose.
I tried the new V5 and the SDMA clock is in perfect sync with combel now. BUT, a under-sight was when the CT60 is removed, it changes the timing again. So I have done a new design with a fixed delay rather than syncing to the EXP clock.
Sync can be taken from the SDMA pin directly, but its adding another wire.. which will add another delay anyway. So I think having a fixed timing is likely the best solution. However, as this is all a turned circuit. Every falcon is likely different.. So even with a PLL, obtaining a perfect sync isn't simple. You have a 4ns delay tot he SDMA, so a direct wire may have 2ns for the feedback. So there is no point in trying to compensate for 2 delays which will have random timings anyway.
But even so, I am skeptical the clock sync with the SDMA is the root cause of peoples CT60 issues. I have had various timings on mine and never seen any hard crashing. So I personally would lean more towards bus stability issues.