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Re: DFB1 based-design clone

Posted: 24 Apr 2023 09:41
by TotO
Another question, related to the Falcon COMBEL/VIDEL/DMA 16-bit bus:
If the expansion CPU run at 32MHz, does it access them at this speed, or it is limited to "16MHz" for any reason?

Thank you.

Re: DFB1 based-design clone

Posted: 24 Apr 2023 11:26
by exxos
TotO wrote: 24 Apr 2023 09:41 Another question, related to the Falcon COMBEL/VIDEL/DMA 16-bit bus:
If the expansion CPU run at 32MHz, does it access them at this speed, or it is limited to "16MHz" for any reason?

Thank you.
@Badwolf Would be better to answer. But as far as I'm aware, the booster still accesses the system at 16MHz. It can give the impression it is running faster because the CPU cache can run at higher speeds though.. EG 33MHz / 50MHz etc.

You basically have two look at it that the faster CPU can only really talk to the RAM on the booster at full speed. Because that is a bit of an over generalisation.. But that is basically the easiest way to look at it.

Re: DFB1 based-design clone

Posted: 24 Apr 2023 12:00
by TotO
exxos wrote: 24 Apr 2023 11:26You basically have two look at it that the faster CPU can only really talk to the RAM on the booster at full speed. Because that is a bit of an over generalisation.. But that is basically the easiest way to look at it.
Well, ok. Because Combel and Videl are clocked to 32MHz, I have expected the bus was limited to 16MHz, only because the CPU clock.

Re: DFB1 based-design clone

Posted: 24 Apr 2023 14:39
by exxos
TotO wrote: 24 Apr 2023 12:00
exxos wrote: 24 Apr 2023 11:26You basically have two look at it that the faster CPU can only really talk to the RAM on the booster at full speed. Because that is a bit of an over generalisation.. But that is basically the easiest way to look at it.
Well, ok. Because Combel and Videl are clocked to 32MHz, I have expected the bus was limited to 16MHz, only because the CPU clock.
Afraid I cannot answer that because I'm not that familiar with the Falcon personally.

But generally the chips issue DTACK to the CPU, so if the CPU runs at higher speeds, its still stuck waiting from DTACK from the chipset anyway.

Re: DFB1 based-design clone

Posted: 24 Apr 2023 19:44
by mikro
TotO wrote: 24 Apr 2023 12:00Because Combel and Videl are clocked to 32MHz, I have expected the bus was limited to 16MHz, only because the CPU clock.
Isn't that the other way around? I.e. there's one master 32 MHz clock which is then divided for the CPU, SDMA etc (16 MHz) and fed to Videl, DSP etc (32 MHz) ? So if you replace the crystal with a 50 MHz one, CPU still gets only 25 MHz.

Of course, nothing stops you to overclock CPU/FPU with a separate clock but then you lose the balance between the Blitter, CPU, FPU and DSP and a lot of demos stops working. :)

Re: DFB1 based-design clone

Posted: 24 Apr 2023 20:16
by TotO
mikro wrote: 24 Apr 2023 19:44Isn't that the other way around? I.e. there's one master 32 MHz clock which is then divided for the CPU, SDMA etc (16 MHz) and fed to Videl, DSP etc (32 MHz) ? So if you replace the crystal with a 50 MHz one, CPU still gets only 25 MHz. Of course, nothing stops you to overclock CPU/FPU with a separate clock but then you lose the balance between the Blitter, CPU, FPU and DSP and a lot of demos stops working. :)
What I mean is by using an expansion CPU not the internal overclocked. You are right, the DMA circuit is clocked by the DSP (32MHz) and the "CPU" (16MHz). So, it looks to be this circuit that rhythm the system and explain what we know about 16/25MHz bus speed.

EDIT: The schematic show the cpuclocka (FPU) connected to the DMA and not the cpuclkb (CPU) as expected. A mistake?

Re: DFB1 based-design clone

Posted: 24 Apr 2023 21:25
by mikro
No, no, nothing like that. :)

The Master Clock (TM) comes to the Combel (32 MHz). Then there's CPUCLK0 (16 MHz) which branches into R221, R222 and R216 and going to:

- CPU
- Expansion slot
- SDMA and FPU

That's what I wanted to say -- if you overclock Combel to 50 MHz, you get only half on the CPUCLK0 = 25 MHz. So it's not like CPU/FPU is forcing anything, it's Combel's "decision" to clock the bus this way.

Re: DFB1 based-design clone

Posted: 24 Apr 2023 21:47
by TotO
mikro wrote: 24 Apr 2023 21:25No, no, nothing like that. :)
We are not saying something different. :)

Re: DFB1 based-design clone

Posted: 24 Apr 2023 22:21
by mikro
Perhaps I misunderstood then - I was under impression that you said that the DMA IC is the clock source (which is not, the Combel is), my bad.

Re: DFB1 based-design clone

Posted: 25 Apr 2023 08:21
by TotO
mikro wrote: 24 Apr 2023 22:21 Perhaps I misunderstood then - I was under impression that you said that the DMA IC is the clock source (which is not, the Combel is), my bad.
I just said that I have understood the DMA IC define the bus speed. Thank you. (I don't speak about the clock source). :)
Sure, because COMBEL generate the clock provided to the DMA IC, it can be changed from here, but it is not what I wanted to know.