Atari STF/STFM and Mega ST FastROM/FastTOS technical info please
Posted: 09 Jun 2025 08:39
Dear All.
I have been looking into how FastROM can be activated, mainly on the Mega ST motherboard. Some of the research I have done says the ST has 0 wait states (for ROM), yet some info says that there is a ROM delay. My HBS240 accelerator board has jumpers for 0,1,2 wait states, when set to 0, and the CPU running at 16Mhz, the FastROM result is as expected. However, some of my accelerators don't have FastROM jumpers, so I was wondering if anybody can explain to me how this could be achieved?
I have 45ns and 70ns ROM chips in place. They made a fractional difference, but not the desired difference, i.e Gembench 6 reports around 170% (no CPU cache)when successful, as does the Exxos 16Mhz booster with FastROM enabled.
I have read some Exxos info about when he/they were developing the 32Mhz CPU/FastROM booster for the STE. It talked about changing a resistor and/or reprogramming a GAL chip to control ROM speed/delay.
Can anyone please give me some 'easy to understand' technical info? I could be out of my depth here, but eager to learn still. Many thanks.
Regards James
I have been looking into how FastROM can be activated, mainly on the Mega ST motherboard. Some of the research I have done says the ST has 0 wait states (for ROM), yet some info says that there is a ROM delay. My HBS240 accelerator board has jumpers for 0,1,2 wait states, when set to 0, and the CPU running at 16Mhz, the FastROM result is as expected. However, some of my accelerators don't have FastROM jumpers, so I was wondering if anybody can explain to me how this could be achieved?
I have 45ns and 70ns ROM chips in place. They made a fractional difference, but not the desired difference, i.e Gembench 6 reports around 170% (no CPU cache)when successful, as does the Exxos 16Mhz booster with FastROM enabled.
I have read some Exxos info about when he/they were developing the 32Mhz CPU/FastROM booster for the STE. It talked about changing a resistor and/or reprogramming a GAL chip to control ROM speed/delay.
Can anyone please give me some 'easy to understand' technical info? I could be out of my depth here, but eager to learn still. Many thanks.
Regards James