exxos's Atari, Amiga & retro forum

A few weeks ago I picked up a William Stuart Systems ZX81 sound card as part of the haul from an old school friend.

It's in a bit of a mess as all the pads and some of the traces around where the edge connector was have been pulled away.


I've managed to trace everything and make a new schematic (slightly modified to use pin headers for the I/O and sound)...


However, the address decode logic is completely perplexing. How on Earth do you do address decoding using NOR gates?

Can any of you make head or tail of this?

stephen_usher wrote: 05 Jun 2025 16:48
It's in a bit of a mess as all the pads and some of the traces around where the edge connector was have been pulled away.

This seems to be a theme at the moment..

I did once build a sound card based on a latch card, it was a bit feeble but it did work, might be similar in decoding, I might have the schematic for the latch card still if you want to see it?

I do have a zx81 sound card "somewhere". I bought it ages ago and forgot id got it. I'll try and find it and see if that helps?

My friend had obviously done this "in antiquity" and he'd soldered a ribbon cable to various points on the board. The ribbon cable went no-where as it had been cut. Inside the box to hold the ZX81 (and keyboard) there was an edge connector going up to a switch and pot plus a speaker. Obviously he'd had the sound card fitted in there at some time somehow.

Hmm, looks like the latch card schematic is a bust, no schematic, just a wiring table...

What do you mean?

stephen_usher wrote: 05 Jun 2025 17:10 What do you mean?

I have an old Sinclair magazine with a latch card build and thought it had a schematic that might help make sense of addressing.

There is no schematic, just a table of what pins connect to where. If you want an image that's no problem.

Here's what I've got so far...

/A2+WR is only high if it's a write and A2 is low.

This means that /RD+A2_WR is low if the above is true and it's a read operation, but that would mean it would almost always be high. *eh*

Which means that the AY's BC1 would be almost completely controlled by/IOREQ. The truth table is a bit mind bending.

Maybe it's using the NOR gates as NAND gates in some way? As in the output is only low if all the inputs are low.

OK, I think the AY BC1 is low: Write and !A2 and !read and IOREQ is enabled. (?)
AY BDIR is if it's an I/O request and a write.
AY-A8 is only low if it's an I/O request and A3 and A4 are low.

Sound reasonable?

Actually... is it using I/O ports 0 and 4?