exxos's Atari, Amiga & retro forum

Hi,

i have an STE CA4003290 which has had a really shitty cap jib done before i got it.

all the baps have been reconnected to there relevant traces and now when powered i get a black screen.

the reset circuit is working fine.
the 68000 is in halt on pin 19, the cpu has been swapped into a working board and is fully working.
there were no roms and a set on tos 2.06 has been made and tested for the board, W102, W103 and W104 have been set for the 27c1001s that have been installed.
on the schematics pin 19(halt) connects to pin 4(U210 74ls06 - tested) and pin 2(P100 1.2k RN) then it goes off with XHALT but i am unable to find out where XHALT goes to.
there is no serial output from the diag cart either which i would expect with the cpu in halt.
the installed 4mb ram has also been tested in another STE.
this board has U101 fitted with R111 and R112 not installed as per the schematics.
U100 pin 15 has clock
with the shifter chip(U401) removed the cpu comes out of half, this has been tested in another STE and is working fine.

would anyone know where the XHALT goes to as the halt line is being pulled to 0v, pin 24(BERR) is hi so not in buss error.

any help would be appreciated.

It's as you wrote, XHALT links U210 pin #4 (fed by pin #3 which is the reset circuit) to the CPU /HALT pin, with a pull up with P100 pin #2). I did not find more.

the thing that gets me is the XHALT goes off but doesnt re-apear on the schematic.

It doesn't appear again, no, I did an AI search and that is all there is in that schematic.

i found P100 to P105 had broken connections, they have now been fixed and the cpu is out of HALT.

when powering on i get activifty for a few seconds then it stops.
the diag cart is still not starting.

the serial connection to the pc het a characvture (the same one) every now and again when switching on, getting more now so must be getting closer to fixing it.

And now starts the tedious work of checking continuity along all the traces (data, address, control sgnals etc...)

sporniket wrote: 13 May 2025 12:41 And now starts the tedious work of checking continuity along all the traces (data, address, control sgnals etc...)

yes indeed it does

Evening all,

Was this ever solved? I have an STE with the same problem.