DSTB1: testers for rev 2 firmware (requires modding a rev 1)
Posted: 19 Aug 2024 14:16
Is there anybody with an existing rev 1 DSTB1 who'd like to test out the rev 2 firmware and let me know how they get on before I commit to the final design?
I'm going to put here the current instructions for moddling a rev 1 board to the proposed rev 2 format and the proposed JED to flash to the CPLD.
These mods are revertable should you wish.
NB. You may wish to consider not doing this if you have used a 5V oscilaltor as it involves driving the clock pin of the SDRAM directly from the OSC. I'd have thought damage unlikely at that frequency, but please be warned.
Here is the experimental JED file. I suggest flashing this before performing the board modifications. If you do this after the mods, flash as soon as possible after power-on to avoid any damage from the new wiring.
Two traces need to be cut. One is a short branch to a via that simply holds the SDRAM's CKE pin high. We'll be driving that in rev2.
The second is a tiny connection between the input and output BG lines between the 68k header and socket. We'll be tapping both those pins.
I have modified my two test boards without needing to remove any components using just a dart (as in dartboard) to scrape away the undesired copper.
Here are the points:-
Next, four bodge wires need to be added.
The first two go to the now isolated BG pins. I'll call them BG_IN for the socket (that the 68k chip sits in) and BG_OUT for the pin that goes to the motherboard. These are to be routed to TP5 and TP4, respectively. I found it easiest to route one on the top and one on the bottom of the board, as that's where the pins are exposed. Kynar wire fitted though the gaps in the socket strip for me.
The second two are trickier. You need to tack a wire onto that CKE pin we isolated earlier and also on the CLK pin directly next to it.
The CLK bodge goes to the output pad of the oscillator, which is the south-east pin, looking at the board with pin 1 at the top.
The CKE bodge wire then goes to TP3.
TP1 remains active as a TOS206 CE line.
TP2 is now an output. It should have nothing attached at the moment. If you were using this as an input for an 8MHz switch, please disconnect this. 8MHz mode can now be controlled in software.
I will try to add some more photos of the bodge wire application later on.
As part of these changes you'll need to use new driver software. EmuTOS will no longer auto-recognise the AltRAM as I've decided immitating another card is a bad idea in the long term. If everything proves stable I may submit a patch to the ET team in due course.
You may find the software here:- https://github.com/dh219/DSTB-tools/tre ... /altramset
AltROM is very experimental but can have some good effects if used well -- by default it copies your system ROM to AltRAM giving you a 2x speed boost for ROM calls. It may argue with the blitter as I've only just re-added blitter support and haven't tested that thoroughly, however. You can only deactivate it by power down.
If you try this, good luck and keep me posted.
:thanksyellow:
BW
I'm going to put here the current instructions for moddling a rev 1 board to the proposed rev 2 format and the proposed JED to flash to the CPLD.
These mods are revertable should you wish.
NB. You may wish to consider not doing this if you have used a 5V oscilaltor as it involves driving the clock pin of the SDRAM directly from the OSC. I'd have thought damage unlikely at that frequency, but please be warned.
Here is the experimental JED file. I suggest flashing this before performing the board modifications. If you do this after the mods, flash as soon as possible after power-on to avoid any damage from the new wiring.
Two traces need to be cut. One is a short branch to a via that simply holds the SDRAM's CKE pin high. We'll be driving that in rev2.
The second is a tiny connection between the input and output BG lines between the 68k header and socket. We'll be tapping both those pins.
I have modified my two test boards without needing to remove any components using just a dart (as in dartboard) to scrape away the undesired copper.
Here are the points:-
Next, four bodge wires need to be added.
The first two go to the now isolated BG pins. I'll call them BG_IN for the socket (that the 68k chip sits in) and BG_OUT for the pin that goes to the motherboard. These are to be routed to TP5 and TP4, respectively. I found it easiest to route one on the top and one on the bottom of the board, as that's where the pins are exposed. Kynar wire fitted though the gaps in the socket strip for me.
The second two are trickier. You need to tack a wire onto that CKE pin we isolated earlier and also on the CLK pin directly next to it.
The CLK bodge goes to the output pad of the oscillator, which is the south-east pin, looking at the board with pin 1 at the top.
The CKE bodge wire then goes to TP3.
TP1 remains active as a TOS206 CE line.
TP2 is now an output. It should have nothing attached at the moment. If you were using this as an input for an 8MHz switch, please disconnect this. 8MHz mode can now be controlled in software.
I will try to add some more photos of the bodge wire application later on.
As part of these changes you'll need to use new driver software. EmuTOS will no longer auto-recognise the AltRAM as I've decided immitating another card is a bad idea in the long term. If everything proves stable I may submit a patch to the ET team in due course.
You may find the software here:- https://github.com/dh219/DSTB-tools/tre ... /altramset
AltROM is very experimental but can have some good effects if used well -- by default it copies your system ROM to AltRAM giving you a 2x speed boost for ROM calls. It may argue with the blitter as I've only just re-added blitter support and haven't tested that thoroughly, however. You can only deactivate it by power down.
If you try this, good luck and keep me posted.
:thanksyellow:
BW