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CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 19:54
by mrbombermillzy
I apologise if this is trivial but not being a HW guy...
Im wondering if in any of the below implementations, the CPU can access any non STRAM on the Atari ST when there is another bus master active (e.g. DMA/blitter).
I understand on a standard ST(FM) machine, the CPU just gets halted.
But what about:
1. A machine with ALTRAM? (i.e. AlanH's MonSTer board)
2. A machine with TTRAM on an 020/030 board? (e.g. TF536)
Can any of the above be accessed by the CPU?
Any help would be much appreciated.
Re: CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 20:33
by sporniket
My understanding is that when the CPU grant the bus to another master, it then only can wait for the bus to be given back.
Because it need the bus to exchange data with altram, and the bus is already in use by the other master.
Re: CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 20:47
by mrbombermillzy
sporniket wrote: 07 Jun 2023 20:33
My understanding is that when the CPU grant the bus to another master, it then only can wait for the bus to be given back.
Because it need the bus to exchange data with altram, and the bus is already in use by the other master.
Hi David :)
I was sort of expecting that scenario in the case of ALTRAM board, but with a 030 booster with its own local TTRAM, Im not really sure. (Maybe the MMU dictates the bus activity in this situation?) :shrug:
Re: CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 20:52
by exxos
Technically its possible *if* the 030 has bus isolators to isolate it from the ST bus and accesses TTram. But would maybe need some tweaks to bus arb also to allow the CPU to continue to run during DMA cycles. Not exactly trivial though.
Re: CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 20:54
by Cyprian
mrbombermillzy wrote: 07 Jun 2023 19:54
I apologise if this is trivial but not being a HW guy...
Im wondering if in any of the below implementations, the CPU can access any non STRAM on the Atari ST when there is another bus master active (e.g. DMA/blitter).
I understand on a standard ST(FM) machine, the CPU just gets halted.
But what about:
1. A machine with ALTRAM? (i.e. AlanH's MonSTer board)
2. A machine with TTRAM on an 020/030 board? (e.g. TF536)
Can any of the above be accessed by the CPU?
Any help would be much appreciated.
1) regarding a stock ST, there is only one bus for BLiTTER and CPU, therefore it is not possible to run BLiTTER in ST-RAM and CPU in ALT-RAM/Cartridge ROM/hardware registers at the same time;
2) TF/PAK has two buses - to the ST motherboard (ST-RAM, hardware registers) and its own TT-RAM memory, therefore the CPU can work at the same time in its TT-RAM.
Re: CPU behaviour/bus arbitration of nonstandard ST configurations
Posted: 07 Jun 2023 21:05
by mrbombermillzy
Cyprian wrote: 07 Jun 2023 20:54
1) regarding a stock ST, there is only one bus for BLiTTER and CPU, therefore it is not possible to run BLiTTER in ST-RAM and CPU in ALT-RAM/Cartridge ROM/hardware registers at the same time;
2) TF/PAK has two buses - to the ST motherboard (ST-RAM, hardware registers) and its own TT-RAM memory, therefore the CPU can work at the same time in its TT-RAM.
Ah, so it has 2 buses with regards to a 030 board?
Exactly what I needed to know. :cheers:
Thanks guys.