H6 plan.
Posted: 14 Mar 2021 12:16
I have started working on changes to produce a H6 board now.. I want to produce a board which has "more stuff" and future proof it a bit more. This will of course take some months to complete.
So the current changes are:
1) Add a Audio jack on the rear.
2) Add pads for the RS232 to USB serial module
3) Create 3 variations on 3.3V addon board sizes. 50% larger than 68K and twice the size,to allow more complex addons on a single board.
4) Add a FPGA onboard to allow blitter,glue,mmu to use the suska FPGA cores (The original ST chipset sockets will not be removed)
The FPGA cores will take a lot of time to make cycle accurate. @Icky has made the most cycle accurate blitter core to date. The MMU & GLUE may take some more time as the wakeup states need to be diagnosed properly to allow a typical power up of WS2. We tried to do this with FPGA addon boards on a STFM, but working on original hardware is just a PITA! So I have worked out I will need several more IO buffers to allow interfacing all the extra signals to the FPGA chip.
We know the suska cores work overall. So even if they are not totally cycle accurate, its good enough to do dev work on. Plus as the MMU & GLUE are replaced, it opens the door to a true 32MHz system! OTOH, A faster system will break timings anyway, meaning the wakeup state issue becomes irrelevant anyway.
Though I hope once we get the cores running on CPU & RAM can run at 32MHz and with our FPGA shifter by @Smonson , we are already ready for higher resolutions and colours. We just need faster RAM, and the suska cores in FPGA opens up this door!
So the current changes are:
1) Add a Audio jack on the rear.
2) Add pads for the RS232 to USB serial module
3) Create 3 variations on 3.3V addon board sizes. 50% larger than 68K and twice the size,to allow more complex addons on a single board.
4) Add a FPGA onboard to allow blitter,glue,mmu to use the suska FPGA cores (The original ST chipset sockets will not be removed)
The FPGA cores will take a lot of time to make cycle accurate. @Icky has made the most cycle accurate blitter core to date. The MMU & GLUE may take some more time as the wakeup states need to be diagnosed properly to allow a typical power up of WS2. We tried to do this with FPGA addon boards on a STFM, but working on original hardware is just a PITA! So I have worked out I will need several more IO buffers to allow interfacing all the extra signals to the FPGA chip.
We know the suska cores work overall. So even if they are not totally cycle accurate, its good enough to do dev work on. Plus as the MMU & GLUE are replaced, it opens the door to a true 32MHz system! OTOH, A faster system will break timings anyway, meaning the wakeup state issue becomes irrelevant anyway.
Though I hope once we get the cores running on CPU & RAM can run at 32MHz and with our FPGA shifter by @Smonson , we are already ready for higher resolutions and colours. We just need faster RAM, and the suska cores in FPGA opens up this door!