Magic Dupont wire (clock line termination question)
Posted: 10 Feb 2021 15:15
Need a bit of advice from the grey-beards regarding clock lines, please.
My Falcon board has four clock lines, one low-speed (16MHz) in from the Falcon, one from the oscillator into the CPLD and two leaving the CPLD (one to AltRAM and one to the CPU).
I have no termination on the slow line nor the oscillator to to CPLD and CPLD to AltRAM lines (those are quite short and direct), but my CPU line is fairly tortuously routed.
To that end I've currently got a 330 Ohm resistor to ground at its end. This seems sufficient when running the CPU at speeds of up to 50MHz, but when I bring in the AltRAM (SDRAM running at the same frequency as the CPU but driven by its own pin), it'll work fine at 48MHz, but fails at 50.
If, however, I attach my (cheap and nasty) logic analyser to the CPU clock line, it'll run!
I've tried substituting the analyser with a decade resistance pack without luck, so it doesn't look like a lower end termination resistance is going to be helpful, but if I leave a 12cm bit of Dupont wire hanging off the pin it works again!
5cm of Dupont wire isn't enough. 12cm standing vertically doesn't work, but lay that 12cm length down back across the board and it'll happily run Doom and MiNT (my usual tests).
Can anyone with a bit more experience (or any kind of qualification in!) hardware tell me what's going on here and give me any rule-of-thumb tips as to what termination/anything else I should be doing to these clock lines, please?
My initial thoughts turned to the tiny bit of capacitance the wire/logic analyser could give, but adding capacitance to a clock line worries me -- should it? What else? Inductance? Should I redo the termination to a Thevenin style? Any rules of thumb for values? I think I'll build-in in-line termination pads into the next version, but I wonder how far I can get with this, now.
My target is proper stability at 50. Working at 48 and failing at 50 using parallel termination is a little too close to the bone for me.
Thanks,
BW.
My Falcon board has four clock lines, one low-speed (16MHz) in from the Falcon, one from the oscillator into the CPLD and two leaving the CPLD (one to AltRAM and one to the CPU).
I have no termination on the slow line nor the oscillator to to CPLD and CPLD to AltRAM lines (those are quite short and direct), but my CPU line is fairly tortuously routed.
To that end I've currently got a 330 Ohm resistor to ground at its end. This seems sufficient when running the CPU at speeds of up to 50MHz, but when I bring in the AltRAM (SDRAM running at the same frequency as the CPU but driven by its own pin), it'll work fine at 48MHz, but fails at 50.
If, however, I attach my (cheap and nasty) logic analyser to the CPU clock line, it'll run!
I've tried substituting the analyser with a decade resistance pack without luck, so it doesn't look like a lower end termination resistance is going to be helpful, but if I leave a 12cm bit of Dupont wire hanging off the pin it works again!
5cm of Dupont wire isn't enough. 12cm standing vertically doesn't work, but lay that 12cm length down back across the board and it'll happily run Doom and MiNT (my usual tests).
Can anyone with a bit more experience (or any kind of qualification in!) hardware tell me what's going on here and give me any rule-of-thumb tips as to what termination/anything else I should be doing to these clock lines, please?
My initial thoughts turned to the tiny bit of capacitance the wire/logic analyser could give, but adding capacitance to a clock line worries me -- should it? What else? Inductance? Should I redo the termination to a Thevenin style? Any rules of thumb for values? I think I'll build-in in-line termination pads into the next version, but I wonder how far I can get with this, now.
My target is proper stability at 50. Working at 48 and failing at 50 using parallel termination is a little too close to the bone for me.
Thanks,
BW.