David's Falcon Booster rev 3 -- dabbling with DRAM
Posted: 20 Nov 2020 10:59
Morning all.
Following on from rev 2b of my unnamed Falcon booster which switches an external 68030 up to 48MHz and adds 1MB of 16-bit Alt-RAM (https://www.exxosforum.co.uk/forum/viewt ... =29&t=3422), it's time to move on to rev 3 and give the project a name. I've had a complete lack of ideas, so it's going to be DFB1 -- David's Falcon Booster -- rev 3.
Changes from the rev2 are a switch from Altera to Xilinx CPLDs (this has taken the biggest time), a move to full address bus decoding to allow more features and most significantly a switch from the demonstration 2x512kB SRAM chips to DRAM.
http://www.farnell.com/datasheets/2622018.pdf
I've never worked with DRAM before so would appreciate any tips going. As I understand things, I'll need to take care of the following:
* Proper initialisation of the two chips;
* Triggering the refresh at the appropriate intervals;
* Decoding address bus requests to a two-step row address then column address, plus any bank and chip selects;
* Handling/ignoring/terminating the 'burst';
* Getting the whole variable bus size and caching logic right since I'm now moving up to a 32 bit data bus.
In effect, I've done none of those before, bar a little bit of the logic on the last one to not ruin the cache when reading 8-bit values from the current 16-bit bus but I've routed all the DRAM pins bar the data bus (which goes through level converters to talk to the 030) to the CPLD so I don't repeat the mistake of tying high or low something that I later actually need to control. Hopefully it can all be worked out in firmware, therefore.
I ran out of space on the Altera chips I was using before. I've gone for overkill on the pin-count for these Xilinx ones, but with over twice the number of macrocells available to me, I hope I'll have sufficient logic this time around.
The plan is to try to bring the board up without Alt-RAM, then start working on the initialisation and refresh logic, then perhaps doing the RAS/CAS work for a 16-bit bus and if all that works, move up to the full 32 bits.
Problems I have that are still outstanding from the rev2b board are the co-processors. I've managed to get the onboard FPU to work by jumpering the DS line on pin 3 of GAL U62, but I've not yet worked out whether that could have any ill effects by generating spurious (or opposing) signals. One of my FPUs stopped working a little while later, so I've removed that hack for the time being. The DSP simply doesn't work. Any DSP-enabled software hangs the machine. That'll be my next line of investigation whilst the boards are out.
Like for the DRAM, above, I'd appreciate any tips or feedback on my likely oversights there.
I have started up a GitHub project for this, but there's nothing there yet other than the start of the wiki, with which I'll attempt to document my work.
https://github.com/dh219/DFB/wiki
It's starting to get complicated.
BW aka David.
Following on from rev 2b of my unnamed Falcon booster which switches an external 68030 up to 48MHz and adds 1MB of 16-bit Alt-RAM (https://www.exxosforum.co.uk/forum/viewt ... =29&t=3422), it's time to move on to rev 3 and give the project a name. I've had a complete lack of ideas, so it's going to be DFB1 -- David's Falcon Booster -- rev 3.
Changes from the rev2 are a switch from Altera to Xilinx CPLDs (this has taken the biggest time), a move to full address bus decoding to allow more features and most significantly a switch from the demonstration 2x512kB SRAM chips to DRAM.
http://www.farnell.com/datasheets/2622018.pdf
I've never worked with DRAM before so would appreciate any tips going. As I understand things, I'll need to take care of the following:
* Proper initialisation of the two chips;
* Triggering the refresh at the appropriate intervals;
* Decoding address bus requests to a two-step row address then column address, plus any bank and chip selects;
* Handling/ignoring/terminating the 'burst';
* Getting the whole variable bus size and caching logic right since I'm now moving up to a 32 bit data bus.
In effect, I've done none of those before, bar a little bit of the logic on the last one to not ruin the cache when reading 8-bit values from the current 16-bit bus but I've routed all the DRAM pins bar the data bus (which goes through level converters to talk to the 030) to the CPLD so I don't repeat the mistake of tying high or low something that I later actually need to control. Hopefully it can all be worked out in firmware, therefore.
I ran out of space on the Altera chips I was using before. I've gone for overkill on the pin-count for these Xilinx ones, but with over twice the number of macrocells available to me, I hope I'll have sufficient logic this time around.
The plan is to try to bring the board up without Alt-RAM, then start working on the initialisation and refresh logic, then perhaps doing the RAS/CAS work for a 16-bit bus and if all that works, move up to the full 32 bits.
Problems I have that are still outstanding from the rev2b board are the co-processors. I've managed to get the onboard FPU to work by jumpering the DS line on pin 3 of GAL U62, but I've not yet worked out whether that could have any ill effects by generating spurious (or opposing) signals. One of my FPUs stopped working a little while later, so I've removed that hack for the time being. The DSP simply doesn't work. Any DSP-enabled software hangs the machine. That'll be my next line of investigation whilst the boards are out.
Like for the DRAM, above, I'd appreciate any tips or feedback on my likely oversights there.
I have started up a GitHub project for this, but there's nothing there yet other than the start of the wiki, with which I'll attempt to document my work.
https://github.com/dh219/DFB/wiki
It's starting to get complicated.
BW aka David.