exxos's Atari, Amiga & retro forum

As most of you know I’ve been doing 060 work for a bit.

Wondering what the consensus on 060 startup is?

My design never lets 5V reach the CPU and I’ve been told I’m a idiot for not having clamp diodes to the 5V rail.

My take on it was that since the design is pure 3.3V it wasn’t required but I wanted to gather opinions.

For those mystified I’m referring to the SCR Latch up that can occur at startup when 5V is applied to IO pins before the CPU voltage is at 3.3V.

I suppose it’s possible that 3.3V on IO pins might do damage?

I wouldn't really believe anyone who hasn't made a 68060 accelerator beforehand... The only people who would be qualified to answer this, IMHO, would be Jens, Dave Haynie and perhaps the former Phase5 engineers.

Yeah it was Jens

He’s trying to discredit my board by saying it will blow up 68060 CPUs because 5V overvoltage on the io lines... which I think is rubbish because the CPU never gets 5V io. Always 3.3V. That whole bus is treated like an FPGA is on there...

Would be pretty bad if Xilinx chips had 5V pushing on the 3.3V side on power up, everything would probably blow up :) Sometimes there are "orders" on how to power up chips, normally all this is stated in the pdf's to ensure this type of thing doesn't happen.

Look at the CT60...

http://powerphenix.com/CT60/CT63.jpg

nothing on there.. looks like might be 3 buffers, assume to interface 3.3V to assume 1.8V DIMM voltage.

Latchup is normally on over or undershoots on signals. Though you have to under/over volt for maybe 20ns or more by a couple of volts etc. Normally under/overshoots and durations are defined in the datasheets. I never heard of this happening during power up conditions. Rails are normally powered up within a few ns of each other anyway.

Though as long as you have a ground plane and stay grounded, all should be fine IMO.

terriblefire wrote: 17 Dec 2019 16:10 Yeah it was Jens

He’s trying to discredit my board by saying it will blow up 68060 CPUs because 5V overvoltage on the io lines... which I think is rubbish because the CPU never gets 5V io. Always 3.3V. That whole bus is treated like an FPGA is on there...

Ok, but the 68060 is 5V I/O tollerant by design. So even if you get 5V I/O, so what? I understand that my knowledge is definitely lacking in this area but logically this doesn't seem to make a lot of sense, maybe I am missing something?

Having said that I powered up the whole 68060 at 5V and run it for a bit (don't ask why). It will actually overheat and crash after a while, but it didn't seem to do any permanent damage on the whole.

Did you consult Jens directly or was this some kind of stray comment? There is no doubt that he is a brilliant engineer but your card will undercut his significantly, so it could be anything.

alenppc wrote: 17 Dec 2019 17:54 Ok, but the 68060 is 5V I/O tollerant by design. So even if you get 5V I/O, so what? I understand that my knowledge is definitely lacking in this area but logically this doesn't seem to make a lot of sense, maybe I am missing something?

Having said that I powered up the whole 68060 at 5V and run it for a bit (don't ask why). It will actually overheat and crash after a while, but it didn't seem to do any permanent damage on the whole.

Did you consult Jens directly or was this some kind of stray comment? There is no doubt that he is a brilliant engineer but your card will undercut his significantly, so it could be anything.

No he's publically ranting about my board on a1k.

https://www.a1k.org/forum/index.php?thr ... 870/page-2

I think he's very worried that it will kill sales of his new board. So will say anything.

What he's talking about the time between startup and the 3.3V rail being ready. The 68060 is only 5V tolerant when powered up. Not when its off. So if you pump 5V over its IO pins when its powered down it CAN do damage. Actually the XIlinx 9500 claims the same thing but i've accidentally left it sit on for an hour before and thought the CPLDs would be fried.. but they were fine. I wouldn't recommend it though.

To avoid this situation I NEVER let 5v come directly from the Amiga to the CPU. It always passes through a buffer or CPLD. In the next version i'll probably put split power rails on for CPLD/Buffers and CPU/RAM. But this was a pure prototype and really its not needed to prove the thing works.

EDIT: I mean he's on the verge of threatening me of deliberately trying to kill precious 68060 CPUs.

terriblefire wrote: 17 Dec 2019 18:11

No he's publically ranting about my board on a1k.

https://www.a1k.org/forum/index.php?thr ... 870/page-2

I think he's very worried that it will kill sales of his new board. So will say anything.

Exactly what I thought when I read his comments over on a1k,
your TF1260 is a beast ! and rock solid and works ,mine has been on soak for a solid four days, not missed a beat,
I know a winner when I see one :)

supaduper wrote: 17 Dec 2019 18:47

terriblefire wrote: 17 Dec 2019 18:11

No he's publically ranting about my board on a1k.

https://www.a1k.org/forum/index.php?thr ... 870/page-2

I think he's very worried that it will kill sales of his new board. So will say anything.

Exactly what I thought when I read his comments over on a1k,
your TF1260 is a beast ! and rock solid and works ,mine has been on soak for a solid four days, not missed a beat,
I know a winner when I see one :)

Constructive criticism can be helpful but I find the comments on A1K quite harsh, especially the Matze ones... uninformed and unnecessary. There is a reason why I don't like that board. Just because your scope is different doesn't mean everybody's the same.

alenppc wrote: 17 Dec 2019 19:07 Constructive criticism can be helpful but I find the comments on A1K quite harsh, especially the Matze ones... uninformed and unnecessary. There is a reason why I don't like that board. Just because your scope is different doesn't mean everybody's the same.

Indeed. Matze has a bit of a nerve to call anyone else's HDL gruesome.

For my own learning I tried to look up what Jens is talking about. I think it's section "11.2.1.2 INPUT SIGNALS DURING POWER-UP REQUIREMENT" of the 68060 User Manual

This falls directly within the "11.2 USING AN MC68060 IN AN EXISTING MC68040 SYSTEM" chapter which is not what is going on here. Since your design is 3.3V via the CPLDs I'd just politely ignore him.

I love Jens' hardware but it's definitely on the over-engineered end of the spectrum (which may be justified, as he is running a business) and as you say your design is for the hobbyist and tinkerer.

I think you are right in pointing out the language differences - there are also cultural differences and subtleties that are lost. While he is trying to help there is always going to be a level of elitism as he's been around for a long time and his niche corner of the market had been unchallenged for a long time.

So keep dancing like noone's watching :lol: