exxos's Atari, Amiga & retro forum

I've started a new thread for this as its getting confusing with cross post talks about all this. So please post information in this thread.

To round up so far..

@PaulJ https://www.exxosforum.co.uk/forum/viewt ... =70#p29868 Looking like ACK isn't pulsing.


@Icky has tried jumpering the buffers and made no odds.

I think all 3 of us have checked the H4 schematic and found nothing wrong.

The only changes I made or know of are:

Other than, as Icky said, I used a NOR as a inverter for the MFP input, swapped a LS04 for a LS06 (hence the pull up on HDRQ). I also renamed FDINT to HDINT, but all points look connected the same as the Alpha.

Aside from the buffers (the DMA buffer was tested on a bodge board and literally copy-pasted over) even so, Icky says it still not working jumpered.

The only thing I can think of is if the propagation delays of the chips I swapped about are the issue.. But there isn't any real different anyway. Both swaps are still inverters, so no logic function changes.

Been around it all again, still don't see anything wrong. compared it to the Alpha and STF diagram, unless I am going blind, just nothing wrong circuit wise that I can see.

The only other difference is the case of the DB19 isn't grounded on the H4 ? I don't have a board here to check.

I think we need more peoples builds up and running to test the DMA port as there shouldn't be anything wrong anywhere.

I probably won't get my boards until after xmas, so won't be able to look into it myself :(

I think it would help if someone checks on a scope that all the DMA lines before and after the inverters etc are all looking as expected.


So we have these as potential causes:

• Bad soldering - Which 2 people would have the same soldering issue
• Bad schematic - which 3 or 4 people have checked and found nothing amiss
• Everyone's forgot to plug power into ultrasatan.
• Aliens.

@exxos would you like me to send you my first one?

PhilC wrote: 08 Dec 2019 12:09 @exxos would you like me to send you my first one?

Your not running yet though are you phil ?

exxos wrote: 08 Dec 2019 12:24

PhilC wrote: 08 Dec 2019 12:09 @exxos would you like me to send you my first one?

Your not running yet though are you phil ?

Not yet no but it is assembled as you know. Just thinking what time I have etc.

exxos wrote: 08 Dec 2019 11:53 I've started a new thread for this as its getting confusing with cross post talks about all this. So please post information in this thread.

Good idea. I have been bouncing around @PaulJ and my thread about this.

exxos wrote: 08 Dec 2019 11:53 I think it would help if someone checks on a scope that all the DMA lines before and after the inverters etc are all looking as expected.

I'll have a look now. Finally have some Atari time.

PhilC wrote: 08 Dec 2019 12:27 Not yet no but it is assembled as you know. Just thinking what time I have etc.

ah I have same problem, no time, I need to start on flashyclock tomorrow , so trying not to get side-tracked to much, otherwise it will just keep getting pushed back to the point another year has gone. Then I got the IDE board to finish, the SEC boosters, I just hope my H4 boots when it arrives as I won't have time to debug that either :(

I have been half pondering how to debug the boards even when diagrom doesn't boot, but problem is, it will turn into another project I don't have time for :( But like I said the other day, if people are diverting from the BOM and using other brands of PLCC sockets, then that could may well be the cause of peoples issues. I had a V2 booster board, was basically a PLCC to DIP adapter by the time I finished, everything metered out fine, bugger wouldn't boot. Which was why I ended up in the mess with PLCC sockets. In changing to the 3M branded ones, I've not yet had any odd socket issues since. Fact is the new HC 68000 CPU's will not likely work in any other brand of PLCC socket other than the 3M ones. In which case, people may be better trying to boot from a DIP CPU instead.

Good suggestion with the DIP. I may try that next.

I think to rule out the logic changes I did..

Can someone scope ... Both sides of the inverter, DRQ & HDRQ. Make sure (on a scope not LA!) both signals have a good rise and fall time, and are switching to 0V and to about 5V levels.


Similar with the MFP HDINT signal..

Would also help if the delay between input and output is documented (should be around 12ns) and may also help to verify the same on the Alpha or another STF machine. Document voltages and delay times.

exxos wrote: 08 Dec 2019 13:27 I think to rule out the logic changes I did..

Can someone scope ... Both sides of the inverter, DRQ & HDRQ. Make sure (on a scope not LA!) both signals have a good rise and fall time, and are switching to 0V and to about 5V levels.

Pin 13 (DRQ) is YELLOW line and Pin 12 (HDRQ) is BLUE line. Scope is just after a reset.


EDIT: Better image

BTW: I know that the 74LS245 buffer has been ruled out for this particular problem, but I still wonder how it is ever supposed to work. It uses /HDCS as its enable signal. But /HDCS is not asserted (= constantly high) during the actual data transfer between device and host. /HDCS is only used during the command and status phases of an ACSI transfer, not during the data phase. Therefore, no data can be transferred from or to the device the way the buffer is wired. What am I missing?