Decided to have a look at what it actually "hangs on" . I fed information into a I am gutted to summarise everything into a more comprehensible format... But it looks like for some reason ROM was being accessed but as a WRITE.. Nothing would respond with DTACK and likely why the thing hung up. :stars:
MC68000 Bus Lockup Analysis (Atari ST / TOS 2.06)
While debugging a system lockup I probed a number of pins on the MC68000 CPU and found the following signals held LOW while the clocks were still running.
Pins observed LOW
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Pin 9 - R/W
Pin 23 - IPL2
Pin 24 - IPL1
Pin 26 - FC2
Pin 27 - FC1
Pin 37 - A9
Pin 38 - A10
Pin 41 - A13
Pin 44 - A16
Pin 54 - D15
All other address/data lines were assumed HIGH for the purpose of decoding the bus state.
Decoded address bus
Low address bits observed:
Assuming the remaining address lines are HIGH, the resulting address is approximately:
This falls inside the Atari ST TOS ROM mirror region:
So the CPU is accessing the TOS ROM address space.
Decoded data bus
Only D15 was LOW while the rest were assumed HIGH:
Which corresponds to:
Bus control state
The following control signals were observed:
Meaning the CPU is attempting a:
Function code (CPU state)
Function code lines were:
Which decodes to:
So the cycle type is:
Interrupt level
Interrupt priority lines were:
This corresponds to:
On the Atari ST this interrupt level is generated by the MFP (Multi-Function Peripheral) which handles timers, serial port, floppy signals and other system interrupts.
Combined interpretation
Putting everything together, the CPU appears to be attempting the following bus cycle:
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WRITE 0x7FFF -> Address 0xFEECFF
Space : User Data
Interrupt pending : Level 6
Since this address lies in the TOS ROM region, nothing should acknowledge a write cycle there. If no device asserts DTACK, the MC68000 will simply wait forever for the bus cycle to complete.
This would explain why the CPU appears to be locked on a single repeating bus state.
Possible causes
Typical causes for this type of lockup include:
- Missing DTACK response
- Address decoding fault
- Fault in glue logic
- Data bus floating or stuck bit
- Incorrect ROM shadow / memory mapping logic
Further investigation would require checking the state of the main bus handshake signals such as AS, UDS, LDS, DTACK and BERR to determine exactly which phase of the bus cycle the CPU is stuck in.
EDIT:
Just realised I should have measured all the address bits as it was a 030 cycle. I only could easily access the 68000 DIP bus anyway :roll:
Most likely the CPU was trying to write to SDRAM (or some other high up address which is invalid) as the ST side /AS was not low.